C8051F300 Datasheet, PDF (26/176 Pages) List of Unclassifed Manufacturers – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
Table 3.1. Global Electrical Characteristics (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min Typ Max Units
I_DD Supply Sensitivity (Note 3) F = 25 MHz
F = 1 MHz
— 47 —
%/V
— 59 —
%/V
I_DD Frequency Sensitivity
(Note 3, Note 5)
V_DD = 3.0 V, F <= 1 MHz, T = 25 °C
V_DD = 3.0 V, F > 1 MHz, T = 25 °C
— 0.27 — mA/MHz
— 0.10 — mA/MHz
V_DD = 3.6 V, F <= 1 MHz, T = 25 °C
— 0.35 — mA/MHz
V_DD = 3.6 V, F > 1 MHz, T = 25 °C
— 0.12 — mA/MHz
Digital Supply Current
(Stop Mode, shutdown)
Oscillator not running,
V_DD Monitor Disabled
— < 0.1 —
µA
Notes:
1. Given in Table 10.1 on page 104.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Based on device characterization data; Not production tested.
4. Normal IDD can be estimated for frequencies <= 15 MHz by simply multiplying the frequency of interest by
the frequency sensitivity number for that range. When using these numbers to estimate I_DD for >15 MHz, the
estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity
number.
For example: V_DD = 3.0 V; F = 20 MHz, I_DD = 6.6 mA – (25 MHz – 20 MHz) x 0.16 mA/MHz = 5.8 mA.
5. Idle IDD can be estimated for frequencies <= 1 MHz by simply multiplying the frequency of interest by the
frequency sensitivity number for that range. When using these numbers to estimate Idle I_DD for >1 MHz, the
estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity
number.
For example: V_DD = 3.0 V; F = 5 MHz, Idle I_DD = 3.3 mA – (25 MHz – 5 MHz) x 0.10 mA/MHz = 1.3 mA.
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Rev. 2.8