C8051F300 Datasheet, PDF (27/176 Pages) List of Unclassifed Manufacturers – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F300/1/2/3/4/5
Pin Number
1
Name
VREF /
Type
Description
A In External Voltage Reference Input.
P0.0
D I/O or Port 0.0. See Section 12 for complete description.
A In
2
P0.1
D I/O or Port 0.1. See Section 12 for complete description.
A In
3
V_DD
Power Supply Voltage.
4
XTAL1 /
A In Crystal Input. This pin is the external oscillator circuit return
for a crystal or ceramic resonator. See Section 11.2.
P0.2
D I/O or Port 0.2. See Section 12 for complete description.
A In
5
XTAL2 /
A Out Crystal Input/Output. For an external crystal or resonator,
this pin is the excitation driver. This pin is the external clock
input for CMOS, capacitor, or RC network configurations.
See Section 11.2.
P0.3
D I/O Port 0.3. See Section 12 for complete description.
6
P0.4
D I/O or Port 0.4. See Section 12 for complete description.
A In
7
P0.5
D I/O or Port 0.5. See Section 12 for complete description.
A In
8
C2CK /
D I/O Clock signal for the C2 Development Interface.
RST
D I/O
Device Reset. Open-drain output of internal POR or V_DD
monitor. An external source can initiate a system reset by
driving this pin low for at least 10 µs.
9
P0.6 /
D I/O or Port 0.6. See Section 12 for complete description.
A In
CNVSTR
D I/O ADC External Convert Start Input Strobe.
10
C2D /
D I/O Data signal for the C2 Development Interface.
P0.7
D I/O or Port 0.7. See Section 12 for complete description.
A In
11
GND
Ground.
Rev. 2.8
27