SI53320-28 Datasheet, PDF (8/51 Pages) Silicon Laboratories – Output Enable option

Si53320-28 Data Sheet
Functional Description
2.5 Output Clock Termination Options
The recommended output clock termination options for dc and ac are shown below. Unused outputs should be left unconnected.
DC Coupled LVPECL Output Termination Scheme 1
VDDO
VDDXX
Si5332x
Q
Qb
R1
50
50
R2
3.3 V LVPECL: R1 = 127 Ohm; R2 = 82.5 Ohm
2.5 V LVPECL: R1 = 250 Ohm; R2 = 62.5 Ohm
R1
VDD = VDDO
LVPECL
Receiver
R2
VTERM = VDDO – 2 V
R1 // R2 = 50 Ohm
DC Coupled LVPECL Output Termination Scheme 2
VDDXX
Si5332x
Q
50
Qb
50
50
VDD = VDDO
LVPECL
Receiver
50
VTERM = VDDO – 2 V
Note:
For Si53320/21/22/23/25/26, VDDXX = VDD = 3.3 V, 2.5 V
For Si53327/28, VDDXX = VDDOA or VDDOB = 3.3 V, 2.5 V
Figure 2.6. LVPECL DC Output Terminations
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