SI53320-28 Datasheet, PDF (17/51 Pages) Silicon Laboratories – Output Enable option

Si53320-28 Data Sheet
Electrical Specifications
Table 3.4. Output Characteristics (LVPECL)
V_DD = 2.5 V ± 5% or 3.3 V ± 10%; T_A = –40 to 85 °C
Parameter
Symbol
Test Condition
Single-Ended Output Swing¹
V_SE
Output Common Mode Voltage
V_COM
Note:
1. Unused outputs can be left floating. Do not short unused outputs to ground.
Min
Typ
Max
Unit
0.55
0.80
1.05
V
V_DD – 1.595
—
V_DD – 1.245
V
Table 3.5. AC Characteristics
V_DD = 2.5 V ± 5% or 3.3 V ± 10%; T_A = –40 to 85 °C
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si53326/28
dc
—
200
MHz
Frequency
F
Si53320
dc
—
725
MHz
Si53321/22/23/25/27
dc
—
1250
MHz
Duty Cycle
(50% input duty cycle)
20/80% T_R/T_F<10% of period
(Differential input clock)
47
50
53
%
D_C
20/80% T_R/T_F<10% of period
(Single-Ended input clock)
45
50
55
%
Minimum Input Clock Slew Rate
SR_diff
SR_se
Required to meet prop delay
0.75
—
and additive jitter specifications
(20–80%)
1.00
—
—
V/ns
—
V/ns
Output Rise/Fall Time
T_R/T_F
20–80%
—
—
350
ps
Minimum Input Pulse Width
T_W
360
—
—
ps
Propagation Delay
T_PLH, T_PHL
600
800
1000
ps
Output-to-Output Skew¹
T_SK
—
25
60
ps
Part-to-Part Skew²
T_PS
—
—
150
ps
10 kHz sinusoidal noise
—
–65
—
dBc
Power Supply Noise Rejection³
PSRR
100 kHz sinusoidal noise
500 kHz sinusoidal noise
—
–62.5
—
dBc
—
–60
—
dBc
1 MHz sinusoidal noise
—
–55
—
dBc
Note:
1. Output-to-output skew specified for outputs with identical configuration.
2. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and equal load con-
dition. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
3. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to V_DD (3.3 V = 100 mV_PP) and noise spur amplitude meas-
ured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for more information.
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