SI53320-28 Datasheet, PDF (30/51 Pages) Silicon Laboratories – Output Enable option

5.4 Si53323 Pin Descriptions
GND 1
CLK_SEL 2
CLK1 3
CLK1b 4
GND
PAD
Si53323
16-QFN
12 ^Q1b
11 Q1
10 Q0b
9 Q0
Si53320-28 Data Sheet
Pin Descriptions
Table 5.4. Si53323 16-QFN Pin Descriptions
Pin
Name
Type¹
Description
1
GND
GND
Ground.
2
CLK_SEL
I
Mux input select pin (LVCMOS). When CLK_SEL is high, CLK1 is selected. When
CLK_SEL is low, CLK0 is selected. CLK_SEL contains an internal pull-down resistor.
3
CLK1
I
Input clock 1.
4
CLK1b
I
Input clock 1 (complement). When CLK1 is driven by a single-ended input, connect
CLK1b to an appropriate bias voltage (e.g., for a CMOS input apply V_DD/2).
5
VDD
P
Core and Output Voltage Supply. Bypass with 1.0 µF capacitor and place as close to the
VDD pin as possible.
6
CLK0
I
Input Clock 0.
7
CLK0b
I
Input Clock 0 (complement). When CLK0 is driven by a single-ended input, connect
CLK0b to an appropriate bias voltage (e.g., for a CMOS input apply V_DD/2).
8
NC
—
No connect. Leave this pin unconnected.
9
Q0
O
Output Clock 0.
10
Q0b
O
Output Clock 0 (complement).
11
Q1
O
Output Clock 1.
12
Q1b
O
Output Clock 1 (complement).
13
Q2
O
Output Clock 2.
14
Q2b
O
Output Clock 2 (complement).
15
Q3
O
Output Clock 3.
16
Q3b
O
Output Clock 3 (complement).
GND Pad
Exposed
ground pad
GND
Power supply ground and thermal relief. The exposed ground pad is thermally connected
to the die to improve the heat transfer out of the package. The ground pad must be con-
nected to GND to ensure device specifications are met.
Note:
1. I = Input; O = Output; P = Power; GND = Ground.
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