SI53320-28 Datasheet, PDF (29/51 Pages) Silicon Laboratories – Output Enable option

5.3 Si53322 Pin Descriptions
GND 1
NC 2
NC 3
NC 4
GND
PAD
Si53322
16-QFN
12 ^Q1b
11 Q1
10 Q0b
9 Q0
Si53320-28 Data Sheet
Pin Descriptions
Table 5.3. Si53322 16-QFN Pin Descriptions
Pin
Name
Type¹
Description
1
GND
GND
Ground.
2
NC
—
No connect. Leave this pin unconnected.
3
NC
—
No connect. Leave this pin unconnected.
4
NC
—
No connect. Leave this pin unconnected.
5
VDD
P
Core and Output voltage supply. Bypass with 1.0 µF capacitor and place as close to the
VDD pin as possible.
6
CLK
I
Input Clock
7
CLKb
I
Input clock (complement). When CLK is driven by a single-ended LVCMOS input, con-
nect CLKb to an appropriate bias voltage (e.g. V_DD/2).
8
NC
—
No connect. Leave this pin unconnected.
9
Q0
O
Output Clock 0.
10
Q0b
O
Output Clock 0 (complement).
11
Q1
O
Output Clock 1.
12
Q1b
O
Output Clock 1 (complement).
13
NC
—
No connect. Leave this pin unconnected.
14
NC
—
No connect. Leave this pin unconnected.
15
NC
—
No connect. Leave this pin unconnected.
16
NC
—
No connect. Leave this pin unconnected.
GND Pad
Exposed
ground pad
GND
Power supply ground and thermal relief. The exposed ground pad is thermally connected
to the die to improve the heat transfer out of the package. The ground pad must be con-
nected to GND to ensure device specifications are met.
Note:
1. I = Input; O = Output; P = Power; GND = Ground.
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