SI53320-28 Datasheet, PDF (7/51 Pages) Silicon Laboratories – Output Enable option

Si53320-28 Data Sheet
Functional Description
2.3 Input Bias Resistors
Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected. The non-inverting
input is biased with a 18.75 kΩ pull-down to GND and a 75 kΩ pull-up to V_DD. The inverting input is biased with a 75 kΩ pull-up to V_DD.
VDD
RPU
RPU
+
CLK0 or RPD
CLK1
–
RPU = 75 k
RPD = 18.75 k
Figure 2.5. Input Bias Resistors
Note: To minimize the possibility of system noise coupling into the Si5332x differential inputs and adversely affecting the buffered out-
put, Silicon Labs recommends 1 PPS clocks and disabled/gapped clocks be dc-coupled and driven “stop-low”.
2.4 Input Mux
The Si53320/21/23/26/27/28 provide two clock inputs for applications that need to select between one of two clock sources. The
CLK_SEL pin selects the active clock input. The following table summarizes the input and output clock based on the input mux and
output enable pin settings.
Table 2.3. Input Mux Logic
CLK_SEL
CLK0
CLK1
Q¹
Qb
L
L
X
L
H
L
H
X
H
L
H
X
L
L
H
H
X
H
H
L
Note:
1. On the next negative transition of CLK0 or CLK1.
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