SI53320-28 Datasheet, PDF (27/51 Pages) Silicon Laboratories – Output Enable option

Si53320-28 Data Sheet
Pin Descriptions
Table 5.2. Si53321 32-QFN/32-eLQFP and Si53326 32-QFN Pin Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Name
VDD
CLK_SEL
CLK0
CLK0b
(Si53321 only)
NC
(Si53326 only)
NC
CLK1
CLK1b
(Si53321 only)
NC
(Si53326 only)
GND
VDD
Q9b
Q9
Q8b
Q8
Q7b
Q7
VDD
Q6b
Q6
Q5b
Q5
Q4b
Q4
Q3b
Q3
VDD
Q2b
Type¹
P
I
I
I
Description
Core and Output voltage supply. Bypass with 1.0 µF capacitor and place as close to the
VDD pin as possible.
Mux input select pin (LVCMOS). When CLK_SEL is high, CLK1 is selected. When
CLK_SEL is low, CLK0 is selected. CLK_SEL contains an internal pull-down resistor.
Input clock 0.
Input clock 0 (complement). When CLK0 is driven by a single-ended LVCMOS input,
connect CLK0b to an appropriate bias voltage (e.g. V_DD/2).
—
No connect. Leave this pin unconnected.
No connect. Leave this pin unconnected.
I
Input clock 1.
I
Input clock 1 (complement). When CLK1 is driven by a single-ended input, connect
CLK1b to V_DD/2.
—
No connect. Leave this pin unconnected.
GND
P
O
O
O
O
O
O
P
O
O
O
O
O
O
O
O
P
O
Ground.
Core and Output voltage supply. Bypass with 1.0 µF capacitor and place as close to the
VDD pin as possible.
Output clock 9 (complement).
Output clock 9.
Output clock 8 (complement).
Output clock 8.
Output clock 7 (complement).
Output clock 7.
Core and Output voltage supply. Bypass with 1.0 µF capacitor and place as close to the
VDD pin as possible.
Output clock 6 (complement).
Output clock 6.
Output clock 5 (complement).
Output clock 5.
Output clock 4 (complement).
Output clock 4.
Output clock 3 (complement).
Output clock 3.
Core and Output voltage supply. Bypass with 1.0 µF capacitor and place as close to the
VDD pin as possible.
Output clock 2 (complement).
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