SI53320-28 Datasheet, PDF (25/51 Pages) Silicon Laboratories – Output Enable option

Si53320-28 Data Sheet
Pin Descriptions
Pin #
Name
Type¹
Description
17
CLK1b
I
Input clock 1 (complement). When CLK1 is driven by a single-ended input, connect
CLK1b to an appropriate bias voltage (e.g., for a CMOS input apply V_DD/2).
18
VDD
P
Core and Output voltage supply. Bypass with 1.0 µF capacitor and place as close to the
VDD pin as possible.
19
OEb
Output enable. When OEb = low, the clock outputs are enabled. When OEb = high, Qx is
I
held low and Qxb is held high. OEb features an internal pull-down resistor and may be
left unconnected.
20
VDD
P
Core and Output voltage supply. Bypass with 1.0 µF capacitor and place as close to the
VDD pin as possible.
Note:
1. I = Input; O = Output; P = Power; GND = Ground.
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