SI53320-28 Datasheet, PDF (33/51 Pages) Silicon Laboratories – Output Enable option

5.6 Si53327 and Si53328 Pin Descriptions
Si53320-28 Data Sheet
Pin Descriptions
OEAb 1
Q1b 2
Q1 3
Q0b 4
Q0 5
VDD 6
GND
PAD
Si53327
24-QFN
18 OEBb
17 Q4
16 Q4b
15 Q5
14 Q5b
13 _{CLK_SEL}
OEAb 1
Q1b 2
Q1 3
Q0b 4
Q0 5
VDD 6
GND
PAD
Si53328
24-QFN
18 OEBb
17 Q4
16 Q4b
15 Q5
14 Q5b
13 _{CLK_SEL}
Table 5.6. Si53327 and Si53328 24-QFN Pin Descriptions
Pin
Name
Type¹
Description
Output Enable for Bank A (Q0, Q1, Q2). When OEAb = LOW, outputs Q0, Q1, and Q2
1
OEAb
I
are enabled. This pin contains an active pull-down resistor, and leaving the pin discon-
nected enables the outputs. When OEAb = HIGH, Q0, Q1, and Q2 are disabled.
2
Q1b
O
Output clock 1 (Complement).
3
Q1
O
Output clock 1.
4
Q0b
O
Output clock 0 (complement).
5
Q0
O
Output clock 0.
6
VDD
P
Core voltage supply. Bypass with 1.0 μF capacitor and place as close to the VDD pin as
possible.
7
CLK0
I
Input clock 0. Bypass with 1.0 µF capacitor and place as close to the VDD pin as possi-
ble.
CLK0b
(Si53327 only)
O
Input clock 0 (complement). When CLK0 is driven by a single-ended input, connect
CLK0b to V_DD/2.
8
NC
(Si53328 only)
—
No connect. Leave this pin unconnected.
9
NC
—
No connect. Leave this pin unconnected.
10
NC
—
No connect. Leave this pin unconnected.
11
CLK1
I
Input clock 1.
CLK1b
(Si53327 only)
I
Input clock 1 (complement). When CLK1 is driven by a single-ended input, connect
CLK1b to VDD/2.
12
NC
(Si53328 only)
—
No connect. Leave this pin unconnected.
13
CLK_SEL
I
Mux input select pin. When CLK_SEL=HIGH, CLK1 is selected. When CLK_SEL=LOW,
CLK0 is selected. CLK_SEL contains an internal pull-down resistor.
14
Q5b
O
Output clock 5 (complement).
15
Q5
O
Output clock 5.
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