SI53320-28 Datasheet, PDF (34/51 Pages) Silicon Laboratories – Output Enable option

Si53320-28 Data Sheet
Pin Descriptions
Pin
Name
Type¹
Description
16
Q4b
O
Output clock 4 (complement).
17
Q4
O
Output clock 4.
18
OEBb
Output Enable for Bank B (Q3, Q4, Q5). When OEBb = LOW, outputs Q3, Q4, and Q5
I
are enabled. This pin contains an active pull-down resistor, and leaving the pin discon-
nected enables the outputs. When OEBb = HIGH, Q3, Q4, and Q5 are disabled.
19
VDDOB
P
Output voltage supply—Bank B (Outputs: Q3 to Q5). Bypass with 1.0 µF capacitor and
place as close to the VDDOB pin as possible.
20
Q3b
O
Output clock 3 (complement).
21
Q3
O
Output clock 3.
22
Q2b
O
Output clock 2 (complement).
23
Q2
O
Output clock 2.
24
VDDOA
P
Output voltage supply—Bank A (Outputs: Q0 to Q2). Bypass with 1.0 μF capacitor and
place as close to the VDDOA pin as possible.
GND Pad
Exposed
ground pad
GND
Ground Pad—Power supply ground and thermal relief. The exposed ground pad is ther-
mally connected to the die to improve the heat transfer out of the package. The ground
pad must be connected to GND to ensure device specifications are met.
Note:
1. I = Input; O = Output; P = Power; GND = Ground.
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