SI53320-28 Datasheet, PDF (1/51 Pages) Silicon Laboratories – Output Enable option

Si53320-28 Data Sheet
Low-Jitter LVPECL Fanout Clock Buffers with up to 10 LVPECL
Outputs from Any-Format Input and Wide Frequency Range from
DC up to 1250 MHz
The Si53320–28 family of LVPECL fanout buffers is ideal for clock/data distribution and
redundant clocking applications. These devices feature typical ultra-low jitter character-
istics of 50 fs and operate over a wide frequency range from dc to 725/1250 MHz. Built-
in LDOs deliver high PSRR performance and reduce the need for external components,
simplifying low-jitter clock distribution in noisy environments.
The Si53320–28 family is available in multiple configurations, with some versions offer-
ing a selectable input clock using a 2:1 input mux. Other features include independent
output enable and built-in format translation. These buffers can be paired with the
Si534x clocks and Si5xx oscillators to deliver end-to-end clock tree performance.
KEY FEATURES
• Ultra-low additive jitter: 50 fs rms
• Built-in LDOs for high PSRR performance
• Up to 10 LVPECL Outputs
• Any-format Inputs (LVPECL, Low-power
LVPECL, LVDS, CML, HCSL, LVCMOS)
• Wide frequency range: dc to 1250 MHz
• Output Enable option
• Multiple configuration options
• Dual Bank option
• 2:1 Input Mux operation
• RoHS compliant, Pb-free
• Temperature range: –40 to +85 °C
VDD
Power Supply Filtering
4
CLK0*
CLK1*
CLK_SEL
5
0
1
3
3
4 Outputs
OEb
5 Outputs
VDDOA
OEAb
3 Outputs
3 Outputs
OEBb
VDDOB
Si53323
Si53320
Si53327/28
10
10 Outputs Si53321/26
*Si53326/28 require Single-ended Inputs
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VDD
Power Supply Filtering
CLK
2
2 Outputs Si53322
VDD
Power Supply Filtering
CLK0
5
5 Outputs
Si53325
CLK1
5
5 Outputs
Rev. 1.2