SI53320-28 Datasheet, PDF (24/51 Pages) Silicon Laboratories – Output Enable option

5. Pin Descriptions
5.1 Si53320 Pin Descriptions
Si53320-28 Data Sheet
Pin Descriptions
Q0 1
Q0b 2
Q1 3
Q1b 4
Q2 5
Q2b 6
Q3 7
Q3b 8
Q4 9
Q4b 10
Si53320
20-TSSOP
20 VDD
19 OEb
18 VDD
17 CLK1b
16 CLK1
15 NC
14 CLK0b
13 CLK0
12 CLK_SEL
11 GND
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
Q0
Q0b
Q1
Q1b
Q2
Q2b
Q3
Q3b
Q4
Q4b
GND
CLK_SEL
CLK0
CLK0b
NC
CLK1
Table 5.1. Si53320 20-Pin TSSOP Descriptions
Type¹
O
O
O
O
O
O
O
O
O
O
GND
I
I
I
—
I
Description
Output clock 0.
Output clock 0 (complement).
Output clock 1.
Output clock 1 (complement).
Output clock 2.
Output clock 2 (complement).
Output clock 3.
Output clock 3 (complement).
Output clock 4.
Output clock 4 (complement).
Ground.
Mux input select pin (LVCMOS). When CLK_SEL is high, CLK1 is selected. When
CLK_SEL is low, CLK0 is selected. CLK_SEL contains an internal pull-down resistor.
Input clock 0.
Input clock 0 (complement). When CLK0 is driven by a single-ended input, connect
CLK0b to an appropriate bias voltage (e.g., for a CMOS input apply V_DD/2).
No connect. Leave this pin unconnected.
Input clock 1.
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