SI53320-28 Datasheet, PDF (18/51 Pages) Silicon Laboratories – Output Enable option

Si53320-28 Data Sheet
Electrical Specifications
Table 3.6. Additive Jitter, Differential Clock Input
Input^{1, 2}
Output
Additive Jitter (fs rms, 12
kHz to 20 MHz)³
V_DD
Amplitude V_IN Differential 20% to
Freq (MHz) Clock Format (Single-Ended,
80% Slew Rate Clock Format
Typ
Max
Peak-to-Peak)
(V/ns)
3.3
725
Differential
0.15
0.637
LVPECL
45
95
3.3
156.25
Differential
0.5
0.458
LVPECL
160
185
2.5
725
Differential
0.15
0.637
LVPECL
45
95
2.5
156.25
Differential
0.5
0.458
LVPECL
145
185
Note:
1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Addi-
tive Jitter Performance” for more information.
2. AC-coupled differential inputs.
3. Measured differentially using a balun at the phase noise analyzer input. See Figure 2.9 Differential Measurement Method Using a
Balun on page 10.
Table 3.7. Additive Jitter, Single-Ended Clock Input
Input^{1, 2}
Output
Additive Jitter (fs rms, 12
kHz to 20 MHz)³
V_DD
Amplitude V_IN Single-Ended 20%
Freq (MHz) Clock Format (Single-Ended, to 80% Slew Rate Clock Format
Typ
Max
Peak-to-Peak)
(V/ns)
3.3
156.25
Single-ended
2.18
1
LVPECL
160
185
2.5
156.25
Single-ended
2.18
1
LVPECL
145
185
Note:
1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Addi-
tive Jitter Performance” for more information.
2. DC-coupled single-ended inputs.
3. Measured differentially using a balun at the phase noise analyzer input. See Figure 2.9 Differential Measurement Method Using a
Balun on page 10.
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