SI5345-44-42 Datasheet, PDF (7/62 Pages) Silicon Laboratories – 10-CHANNEL

Si5345/44/42
Table 3. Input Specifications (Continued)
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max
Unit
REFCLK Frequency
f_{IN_REF}
Frequency range for best 48
output jitter performance
— 54
MHz
TCXO frequency for
—
SyncE
applications. Jitter perfor-
mance may be reduced
40 —
MHz
Input Single-ended Volt-
age Swing
V_{IN_SE}
365 — 2000 mVpp_se
Input Differential Voltage
Swing
Slew rate^{2, 3}
V_{IN_DIFF}
SR
365
2500 mVpp_diff
400 — —
V/µs
Input Duty Cycle
DC
40
— 60
%
Notes:
1. Voltage swing is specified as single-ended mVpp.
OUTx
OUTx
Vcm
Vcm
Vpp_se
Vpp_se
Vpp_diff = 2*Vpp_se
2. Imposed for jitter performance.
3. Rise and fall times can be estimated using the following simplified equation: tr/tf_80-20 = ((0.8 – 0.2) x V_{IN_Vpp_se}) / SR
4. This mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz that must be dc-coupled because they
have a duty cycle significantly less than 50%. A typical application example is a low-frequency video frame sync pulse.
Since the input thresholds (V_IL, V_IH) of this buffer are non-standard (0.33 and 0.49 V, respectively) refer to the input
attenuator circuit for dc-coupled pulsed LVCMOS in the Family Reference Manual at: www.silabs.com/
Support%20Documents/TechnicalDocs/Si5345-44-42-RM.pdf. Otherwise, for standard LVCMOS input clocks, use the
Standard Differential or Single-Ended ac-coupled input mode.
Rev. 1.0
7