SI5345-44-42 Datasheet, PDF (52/62 Pages) Silicon Laboratories – 10-CHANNEL

Si5345/44/42
Table 19. Si5345/44/42 Pin Descriptions (Continued)
Pin Name
FINC
FDEC
IN_SEL0
IN_SEL1
RSVD
Pin Number
Pin Type¹
Si5345 Si5344 Si5342
Function
48
—
—
25
—
—
3
3
3
4
37
37
I
Frequency Increment Pin²
This pin is used to step-up the output frequency of a
selected output. The affected output and its frequency
change step size is register configurable. This pin is inter-
nally pulled low and can be left unconnected when not in
use.
I
Frequency Decrement Pin²
This pin is used to step-down the output frequency of a
selected output. The affected output driver and its fre-
quency change step size is register configurable. This pin
is internally pulled low and can be left unconnected when
not in use.
I
Input Reference Select²
I
The IN_SEL[1:0] pins are used in manual pin controlled
mode to select the active clock input as shown in Table 15
on page 31. These pins are internally pulled low.
5
—
—
20
—
—
— Reserved
—
These pins are connected to the die. Leave disconnected.
21
—
—
—
55
—
—
—
56
—
—
—
NC
—
22
22
No Connect
These pins are not connected to the die. Leave discon-
nected.
Notes:
1. I = Input, O = Output, P = Power
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.
4. Refer to the Si5345/44/42 Family Reference Manual for more information on register setting names.
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Rev. 1.0