SI5345-44-42 Datasheet, PDF (42/62 Pages) Silicon Laboratories – 10-CHANNEL

Si5345/44/42
5.8.13. Zero Delay Mode
A zero delay mode is available for applications that require fixed and consistent minimum delay between the
selected input and outputs. The zero delay mode is configured by opening the internal feedback loop through
software configuration and closing the loop externally as shown in Figure 26.
This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the output
drivers. Any one of the outputs can be fed back to the FB_IN pins, although using the output driver that achieves
the shortest trace length will help to minimize the input-to-output delay. The OUT9 and FB_IN pins are
recommended for the external feedback connection. The FB_IN input pins must be terminated and ac-coupled
when zero delay mode is used. A differential external feedback path connection is necessary for best performance.
Note that automatic input clock switching and hitless switching features are not available when zero delay mode is
enabled.
IN0
IN0
IN1
IN1
IN2
IN2
IN3/FB_IN
IN3/FB_IN
÷P₀
÷P₁
÷P₂
÷P₃
Si5345/44/42
DSPLL
PD LPF
÷M
÷R₀
÷N₀ t0
÷R₁
÷N₁ t1
÷R₂
÷N₂ t2
÷N₃ t3
÷R₇
÷N₄ t4
÷R₈
÷R₉
VDDO0
OUT0
OUT0
VDDO1
OUT1
OUT1
VDDO2
OUT2
OUT2
VDDO7
OUT7
OUT7
VDDO8
OUT8
OUT8
VDDO9
OUT9
OUT9
External Feedback Path
Figure 26. Si5345 Zero Delay Mode Setup
5.8.14. Output Divider (R) Synchronization
All the output R dividers are reset to a known state during the power-up initialization period. This ensures
consistent and repeatable phase alignment across all output drivers. Resetting the device using the RST pin or
asserting the hard reset bit will have the same result. Asserting the sync register bit provides another method of re-
aligning the R dividers without resetting the device.
42
Rev. 1.0