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SI5345-44-42 Datasheet, PDF (16/62 Pages) Silicon Laboratories – 10-CHANNEL | |||
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Si5345/44/42
Table 9. I2C Timing Specifications (SCL,SDA)
Parameter
Symbol Test Condition
SCL Clock Frequency
fSCL
SMBus Timeout
â
Hold time (repeated)
START condition
Low period of the SCL
clock
HIGH period of the SCL
clock
Set-up time for a
repeated START condi-
tion
Data hold time
Data set-up time
Rise time of both SDA
and SCL signals
Fall time of both SDA
and SCL signals
Set-up time for STOP
condition
Bus free time between a
STOP and START con-
dition
Data valid time
Data valid acknowledge
time
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
tf
tSU:STO
tBUF
tVD:DAT
tVD:ACK
When Timeout is
Enabled
Min
Max
Standard Mode
100 kbps
â
100
25
35
4.0
â
4.7
â
4.0
â
4.7
â
100
â
250
â
â
1000
â
300
4.0
â
4.7
â
â
3.45
â
3.45
Min
Max
Fast Mode
400 kbps
â
400
25
35
0.6
â
1.3
â
0.6
â
0.6
â
100
â
100
â
20
300
â
300
0.6
â
1.3
â
â
0.9
â
0.9
Unit
kHz
ms
µs
µs
µs
µs
ns
ns
ns
ns
µs
µs
µs
µs
16
Rev. 1.0
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