SI5345-44-42 Datasheet, PDF (1/62 Pages) Silicon Laboratories – 10-CHANNEL

Si5345/44/42
1 0 - C HANNEL, A NY- F REQUENCY, A NY- O UTPUT J ITTER
ATTENUATOR/CLOCK MULTIPLIER
Features
 Generates any combination of output  Optional zero delay mode
frequencies from any input frequency  Fastlock feature for low nominal
 Input frequency range:
bandwidths
Differential: 8 kHz to 750 MHz
 Glitchless on the fly output frequency
LVCMOS: 8 kHz to 250 MHz
changes
 Output frequency range:
 DCO mode: as low as 0.001 ppb steps.
Differential: up to 712.5 MHz
 Core voltage
LVCMOS: up to 250 MHz
V_DD: 1.8 V ±5%
 Ultra-low jitter:
V_DDA: 3.3 V ±5%
<100 fs typ (12 kHz–20 MHz)
 Independent output clock supply pins:
 Programmable jitter attenuation
3.3 V, 2.5 V, or 1.8 V
bandwidth from 0.1 Hz to 4 kHz
 Output-output skew: 20 ps typ


Meets
Highly
G.8262 EEC
configurable
Opt 1, 2 (SyncE)
outputs compatible


with LVDS, LVPECL, LVCMOS, CML,
and HCSL with programmable signal
amplitude

Serial interface: I²C or SPI
In-circuit programmable with
non-volatile OTP memory
ClockBuilder Pro^TM software simplifies
 Status monitoring (LOS, OOF, LOL)
device configuration
 Hitless input clock switching: automatic ^{ Si5345: 4 input, 10 output, 64 QFN}
or manual
 Si5344: 4 input, 4 output, 44 QFN
 Locks to gapped clock inputs
 Si5342: 4 input, 2 output, 44 QFN
 Automatic free-run and holdover
 Temperature range: –40 to +85 °C
modes
 Pb-free, RoHS-6 compliant
Ordering Information:
See section 8
Functional Block Diagram
XTAL
Si5345/44/42 _XA XB
Device Selector Guide
Grade
Si534fA
Si534fB
Si534fC
Si534fD
Max Output Frequency
712.5 MHz
350 MHz
712.5 MHz
350 MHz
Frequency Synthesis Modes
Integer+Fractional
Integer+Fractional
Integer
Integer
IN_SEL
IN0
IN1
IN2
IN3/
FB_IN
÷FRAC
OSC
÷FRAC
÷FRAC
DSPLL
÷FRAC
Optional
External
Feedback
Applications
 OTN Muxponders and Transponders  Carrier Ethernet switches
 10/40/100G networking line cards  SONET/SDH Line Cards
 GbE/10GbE/100GbE Synchronous  Broadcast video
Ethernet (ITU-T G.8262)
 Test and measurement
 ITU-T G.8262 (SyncE) Compliant
Description
These jitter attenuating clock multipliers combine fourth-generation DSPLL and
MultiSynth™ technologies to enable any-frequency clock generation and jitter
attenuation for applications requiring the highest level of jitter performance. These
devices are programmable via a serial interface with in-circuit programmable non-
volatile memory (NVM) so they always power up with a known frequency configuration.
They support free-run, synchronous, and holdover modes of operation, and offer both
automatic and manual input clock switching. The loop filter is fully integrated on-chip,
eliminating the risk of noise coupling associated with discrete solutions. Further, the
jitter attenuation bandwidth is digitally programmable, providing jitter performance
optimization at the application level. Programming the Si5345/44/42 is easy with Silicon
Labs’ ClockBuilder Pro software. Factory preprogrammed devices are also available.
Multi
Synth
Multi
Synth
Multi
Synth
Multi
Synth
Multi
Synth
NVM
I²C/SPI
Control/
Status
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
Rev. 1.0 7/15
Copyright © 2015 by Silicon Laboratories
Si5345/44/42