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SI5345-44-42 Datasheet, PDF (13/62 Pages) Silicon Laboratories – 10-CHANNEL | |||
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Si5345/44/42
Table 6. LVCMOS Clock Output Specifications (Continued)
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = â40 to 85 °C)
Parameter
Symbol
Output Voltage Low1, 2, 3 VOL
LVCMOS Rise and Fall
tr/tf
Times3
(20% to 80%)
Test Condition
Min
VDDO = 3.3 V
OUTx_CMOS_DRV=1
IOL = 10 mA
â
OUTx_CMOS_DRV=2
IOL = 12 mA
â
OUTx_CMOS_DRV=3
IOL = 17 mA
â
VDDO = 2.5 V
OUTx_CMOS_DRV=1
IOL = 6 mA
â
OUTx_CMOS_DRV=2
IOL = 8 mA
â
OUTx_CMOS_DRV=3
IOL = 11 mA
â
VDDO = 1.8 V
OUTx_CMOS_DRV=2
IOL = 4 mA
â
OUTx_CMOS_DRV=3
IOL = 5 mA
â
VDDO = 3.3V
â
VDDO = 2.5 V
â
VDDO = 1.8 V
â
Typ Max Unit
â VDDO V
x 0.15
â
â
â VDDO V
x 0.15
â
â
â VDDO V
x 0.15
â
420 550 ps
475 625 ps
525 705 ps
Notes:
1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer
to the Si5345/44/42 Family Reference Manual for more details on register settings.
2. IOL/IOH is measured at VOL/VOH as shown in the dc test configuration.
3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50 ï PCB trace. A 5 pF
capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.
IOL/IOH
IDDO
Zs
VOL/VOH
OUT
OUT
AC Test Configuration
Trace length 5 inches
50 ï
499 ï
4.7 pF
DC Block
50 ïï probe, scope
56 ï
50 ï
499 ï
4.7 pF
DC Block
50 ïï probe, scope
56 ï
Rev. 1.0
13
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