SI5345-44-42 Datasheet, PDF (15/62 Pages) Silicon Laboratories – 10-CHANNEL

Si5345/44/42
Table 8. Performance Characteristics
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
PLL Loop Bandwidth Pro-
f_BW
gramming Range¹
0.1 — 4000 Hz
Initial Start-Up Time
t_START Time from power-up to when the
—
30
45
ms
device generates free-running clocks
PLL Lock Time²
t_ACQ
f_IN = 19.44 MHz
— 500 600
ms
Output Delay Adjustment t_{DELAY_frac}
f_VCO = 14 GHz
— 0.28 —
ps
t_{DELAY_int}
— 71.4 —
ps
t_RANGE
— ±9.14 —
ns
POR to Serial Interface
Ready³
t_RDY
—
—
15
ms
Jitter Peaking
J_PK
Measured with a frequency plan run- —
— 0.1
dB
ning a 25 MHz input, 25 MHz output,
and a Loop Bandwidth of 4 Hz
Jitter Tolerance
J_TOL
Compliant with G.8262 Options 1 and —
2 Carrier Frequency = 10.3125 GHz
Jitter Modulation
Frequency = 10 Hz
3180
— UI pk-pk
Maximum Phase Tran-
t_SWITCH Only valid for a single switch between —
—
2.8
ns
sient During a Hitless
two input clocks running at the same
Switch
frequency
Pull-in Range
Input-to-Output Delay
Variation
RMS Phase Jitter⁴
_P
— 500 —
ppm
t_IODELAY
—
2
—
ns
t_ZDELAY In Zero Delay Mode. Measured as the — 110 —
ps
time delay difference between the ref-
erence input and the feedback input,
with both clocks running at 10 MHz
and having the same slew rate. The
rise time of the reference input should
not exceed 200 ps in order to meet
this spec.
J_GEN
Integer Mode
12 kHz to 20 MHz
— 0.090 0.140 ps RMS
Fractional Mode
12 kHz to 20 MHz
— 0.130 0.165 ps RMS
Notes:
1. Actual loop bandwidth might be lower; please refer to CBPro for actual value for your frequency plan.
2. Lock Time can vary significantly depending on several parameters, such as bandwidths, LOL tresholds, etc. For this
case, lock time was measured with nominal and fastlock bandwidths set to 100 Hz, LOL set/clear thresholds of 6/0.6
ppm respectively, using IN0 as clock reference by removing the reference and enabling it again, then measuring the
delta time between the first rising edge of the clock reference and the LOL indicator deassertion.
3. Measured as time from valid VDD/VDDA rails (90% of their value) to when the serial interface is ready to respond to
commands.
4. Jitter generation test conditions: f_IN = 19.44 MHz, f_OUT = 156.25 MHz LVPECL, loop bandwidth = 100 Hz.
Rev. 1.0
15