SI5345-44-42 Datasheet, PDF (35/62 Pages) Silicon Laboratories – 10-CHANNEL

Si5345/44/42
5.7.1. Input LOS Detection
The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing
clock edges. Each of the input LOS circuits has its own programmable sensitivity which allows ignoring missing
edges or intermittent errors. Loss of signal sensitivity is configurable using the ClockBuilder Pro utility.
The LOS status for each of the monitors is accessible by reading a status register. The live LOS register always
displays the current LOS state and a sticky register always stays asserted until cleared. An option to disable any of
the LOS monitors is also available.
Monitor
LOS
en
LOLOSS
Live
Sticky
Figure 17. LOS Status Indicators
5.7.2. XA/XB LOS Detection
A LOS monitor is available to ensure that the external crystal or reference clock is valid. By default the output
clocks are disabled when XAXB_LOS is detected. This feature can be disabled such that the device will continue to
produce output clocks when XAXB_LOS is detected.
5.7.3. OOF Detection
Each input clock is monitored for frequency accuracy with respect to a OOF reference which it considers as its
“0_ppm” reference.
This OOF reference can be selected as either:
 XA/XB pins
 Any input clock (IN0, IN1, IN2, IN3)
The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as
shown in Figure 18. An option to disable either monitor is also available. The live OOF register always displays the
current OOF state, and its sticky register bit stays asserted until cleared.
Monitor
en
OOF
Precision
Fast
en
OLOOFS
Live
Sticky
Figure 18. OOF Status Indicator
5.7.3.1. Precision OOF Monitor
The precision OOF monitor circuit measures the frequency of all input clocks to within ±1 ppm accuracy with
respect to the selected OOF frequency reference. A valid input clock frequency is one that remains within the OOF
frequency range which is register configurable from ±2 ppm to ±500 ppm in steps of 2 ppm.
A configurable amount of hysteresis is also available to prevent the OOF status from toggling at the failure
boundary. An example is shown in Figure 19. In this case the OOF monitor is configured with a valid frequency
range of ±6 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0 - IN3) as the 0 ppm OOF
reference instead of the XA/XB pins is available. This option is register configurable.
Rev. 1.0
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