SI5345-44-42 Datasheet, PDF (31/62 Pages) Silicon Laboratories – 10-CHANNEL

48-54MHz
XO
Si5345/44/42
48-54MHz
XO
48-54MHz
XTAL
XA
XB
2xC_L
OSC
2xCL
÷P_REF
100
XA
XB
2xC_L
OSC
2xC_L
÷P_REF
XA
XB
2xC_L
OSC
2xC_L
÷P_REF
Si5345/44/42
Crystal Resonator
Connection
Si5345/44/42
Differential XO
Connection
Si5345/44/42
Single-ended XO
Connection
Figure 13. Crystal Resonator and External Reference Clock Connection Options
5.6. Inputs (IN0, IN1, IN2, IN3)
There are four inputs that can be used to synchronize the DSPLL. The inputs accept both differential and single-
ended clocks. Input selection can be manual (pin or register controlled) or automatic with user definable priorities.
5.6.1. Manual Input Switching (IN0, IN1, IN2, IN3)
Input clock selection can be made manually using the IN_SEL[1:0] pins or through a register. A register bit
determines input selection as pin selectable or register selectable. The IN_SEL pins are selected by default. If
there is no clock signal on the selected input, the device will automatically enter free-run or holdover mode. When
the zero delay mode is enabled, IN3 becomes the feedback input (FB_IN) and is not available for selection as a
clock input.
Table 15. Manual Input Selection Using IN_SEL[1:0] Pins
IN_SEL[1:0]
0
0
0
1
1
0
1
1
Selected Input
Zero Delay
Zero Delay
Mode Disabled Mode Enabled
IN0
IN0
IN1
IN1
IN2
IN2
IN3
Reserved
Rev. 1.0
31