SI5345-44-42 Datasheet, PDF (51/62 Pages) Silicon Laboratories – 10-CHANNEL

Si5345/44/42
Table 19. Si5345/44/42 Pin Descriptions (Continued)
Pin Number
Pin Name
Pin Type¹
Si5345 Si5344 Si5342
Function
Control/Status
INTR
12
33
33
RST
6
17
17
OE
11
12
12
LOL
47
—
—
—
27
27
LOS0
—
—
30
LOS1
—
—
31
LOS2
—
—
35
LOS3
—
—
36
LOS_XAXB —
28
28
O
Interrupt²
This pin is asserted low when a change in device status
has occurred. It should be left unconnected when not in
use.
I
Device Reset²
Active low input that performs power-on reset (POR) of
the device. Resets all internal logic to a known state and
forces the device registers to their default values. Clock
outputs are disabled during reset. This pin is internally
pulled-up and can be left unconnected when not in use.
I
Output Enable²
This pin disables all outputs when held high. This pin is
internally pulled low and can be left unconnected when
not in use.
O
Loss Of Lock (Si5345)²
This output pin indicates when the DSPLL is locked (high)
or out-of-lock (low). It can be left unconnected when not in
use.
O
Loss Of Lock (Si5344/42)³
This output pin indicates when the DSPLL is locked (high)
or out-of-lock (low). It can be left unconnected when not in
use.
O
Loss Of Signal for IN0³
This pin indicate a loss of clock at the IN0 pin when low.
O
Loss Of Signal for IN1³
This pin indicate a loss of clock at the IN1 pin when low.
O
Loss Of Signal for IN2³
This pin indicate a loss of clock at the IN2 pin when low.
O
Loss Of Signal for IN3³
This pin indicate a loss of clock at the IN3 pin when low.
O
Loss Of Signal on XA/XB Pins³
This pin indicates a loss of signal at the XA/XB pins when
low.
Notes:
1. I = Input, O = Output, P = Power
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.
4. Refer to the Si5345/44/42 Family Reference Manual for more information on register setting names.
Rev. 1.0
51