SI5345-44-42 Datasheet, PDF (30/62 Pages) Silicon Laboratories – 10-CHANNEL

Si5345/44/42
Historical Frequency Data Collected
Clock Failure and
Entry into Holdover
time
120s
Programmable historical data window
used to determine the final holdover value
1s,10s, 30s, 60s
Programmable delay
30ms, 60ms, 1s,10s, 30s, 60s
0s
Figure 12. Programmable Holdover Window
When entering holdover, the DSPLL will pull its output clock frequency to the calculated averaged holdover
frequency. While in holdover, the output frequency drift is entirely dependent on the external crystal or external
reference clock connected to the XA/XB pins. If the clock input becomes valid, the DSPLL will automatically exit the
holdover mode and re-acquire lock to the new input clock. This process involves pulling the output clock frequency
to achieve frequency and phase lock with the input clock. This pull-in process is glitchless and its rate is controlled
by the DSPLL or the Fastlock bandwidth.
5.4. External Reference (XA/XB)
An external crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra low jitter
reference clock for the DSPLL and for providing a stable reference for the free-run and holdover modes. A
simplified diagram is shown in Figure 13. The device includes internal XTAL loading capacitors which eliminates
the need for external capacitors and also has the benefit of reduced noise coupling from external sources. Refer to
Table 12 for crystal specifications. A crystal in the range of 48 MHz to 54 MHz is recommended for best jitter
performance. Frequency offsets due to C_L mismatch can be adjusted using the frequency adjustment feature
which allows frequency adjustments of ±200 ppm. The Si5345/44/42 Family Reference Manual provides additional
information on PCB layout recommendations for the crystal to ensure optimum jitter performance.
The device can also accommodate an external reference clock (REFCLK) instead of a crystal. Selection between
the external XTAL or REFCLK is controlled by register configuration. The internal crystal loading capacitors (C_L)
are disabled in this mode. Refer to Table 3 for REFCLK requirements when using this mode. A P_REF divider is
available to accommodate external clock frequencies higher than 54 MHz. Frequencies in the range of 48 MHz to
54 MHz will achieve the best output jitter performance.
5.5. Digitally Controlled Oscillator (DCO) Mode
The output MultiSynths support a DCO mode where their output frequencies are adjustable in pre-defined steps
defined by frequency step words (FSW). The frequency adjustments are controlled through the serial interface or
by pin control using frequency increment (FINC) or decrement (FDEC). A FINC will add the frequency step word to
the DSPLL output frequency, while a FDEC will decrement it. Any number of MultiSynths can be can be updated at
once or independently controlled. The DCO mode is available when the DSPLL is operating in either free-run or
locked mode.
30
Rev. 1.0