SI5345-44-42 Datasheet, PDF (45/62 Pages) Silicon Laboratories – 10-CHANNEL

Si5345/44/42
6. Register Map
The register map is divided into multiple pages where each page has 256 addressable registers. Page 0 contains
frequently accessible registers, such as alarm status, resets, device identification, etc. Other pages contain
registers that need less frequent access such as frequency configuration, and general device settings. A high level
map of the registers is shown in “6.2. High-Level Register Map” . Refer to the Si5345/44/42 Family Reference
Manual for a complete list of register descriptions and settings. Silicon Labs strongly recommends using
ClockBuilder Pro to create and manage register settings.
6.1. Addressing Scheme
The device registers are accessible using a 16-bit address which consists of an 8-bit page address + 8-bit register
address. By default the page address is set to 0x00. Changing to another page is accomplished by writing to the
‘Set Page Address’ byte located at address 0x01 of each page.
6.2. High-Level Register Map
Table 18. High-Level Register Map
16-Bit Address
8-bit Page
Address
8-bit Register
Address Range
00
00
01
02–0A
0B–15
17–1B
1C
1D
2B
2C–E1
E2–E4
FE
01
01
08–3A
41–42
FE
02
01
02–05
08–2F
30
47–6A
6B–72
FE
Content
Revision IDs
Set Page Address
Device IDs
Alarm Status
INTR Masks
Reset controls
FINC, FDEC Control Bits
SPI (3-Wire vs 4-Wire)
Alarm Configuration
NVM Controls
Device Ready Status
Set Page Address
Output Driver Controls
Output Driver Disable Masks
Device Ready Status
Set Page Address
XTAL Frequency Adjust
Input Divider (P) Settings
Input Divider (P) Update Bits
Output Divider (R) Settings
User Scratch Pad Memory
Device Ready Status
Rev. 1.0
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