SI5345-44-42 Datasheet, PDF (61/62 Pages) Silicon Laboratories – 10-CHANNEL

DOCUMENT CHANGE LIST
Revision 0.9 to Revision 0.95
 Removed advanced product information revision
history.
 Updated “8. Ordering Guide” and changed
references to Revision B.
 Updated parametric tables 2, 3, 5, 6, 7, and 8 to
reflect production characterization.
 Updated terminology to align with ClockBuilder Pro
software.
 Corrected Table 3 references and specifications
from “LVCMOS - DC coupled” to “Pulsed CMOS -
DC-Coupled”.
 Corrected Table 9 I²C data hold time specification to
100 ns from 5 µs.
Revision 0.95 to Revision 1.0
 Corrected minimum input frequency spec from 10 to
0.008 MHz.
 Corrected XAXB minimum input voltage swing spec
from 350 to 365 mV.
 Corrected FINC and FDEC update rate from 1 ns to
1 μs.
 Corrected PLL lock time spec to 500 ms typical and
600 ms max.
 Added common-mode voltage spec for 1.8 V LVDS
(Sub-LVDS) in Table 5.
 Updated spec delay time between chip selects in
Tables 10 and 11.
 Removed SPI Tr/Tf from Table 10.
 Corrected AC Test Configuration Schematic.
 Corrected INx voltage swing spec and split into
single-ended and different inputs requirements.
 Added typical crosstalk spec for Si5342 and Si5344.
 Updated pin descriptions for serial interface.
 Updated SPI timing diagrams and spec.
 Updated max IDDOx spec for LVDS output from 17
to 18 mA.
 Updated max normal mode LVPECL output voltage
swing from 950 to 1000 mVpp_se.
 Updated max VCM specs.
 Updated output-to-output skew specification.
Si5345/44/42
Rev. 1.0
61