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SI5345-44-42 Datasheet, PDF (6/62 Pages) Silicon Laboratories – 10-CHANNEL | |||
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Si5345/44/42
Table 3. Input Specifications
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = â40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max
Unit
Standard Differential or Single-Ended - AC Coupled (IN0/IN0, IN1/IN1, IN2/IN2, IN3/IN3, FB_IN/FB_IN)
Input Frequency Range
Voltage Swing1
Slew Rate2, 3
fIN_DIFF
VIN
SR
Differential
0.008
Single-ended/LVCMOS 0.008
Differential AC Coupled 100
fin < 250 MHz
Differential AC Coupled 225
250 MHz < fin < 750 MHz
Single-Ended AC Coupled 100
fin < 250 MHz
400
â 750
MHz
â 250
MHz
â 1800 mVpp_se
â 1800 mVpp_se
â 3600 mVpp_se
ââ
V/µs
Duty Cycle
DC
40
â 60
%
Capacitance
CIN
Pulsed CMOS - DC Coupled (IN0, IN1, IN2, IN3)
Input Frequency
Input Voltage4
fIN_PULSED_CMOS4
VIL
VIH
Slew Rate2, 3
SR
â
2
â
pF
0.008 â 250
â0.2 â 0.33
0.49 â â
400 â â
MHz
V
V
V/µs
Minimum Pulse Width
PW
Pulse Input
1.6
â
â
ns
Input Resistance
RIN
REFCLK (applied to XA/XB)
â
8
â
kï
Notes:
1. Voltage swing is specified as single-ended mVpp.
OUTx
OUTx
Vcm
Vcm
Vpp_se
Vpp_se
Vpp_diff = 2*Vpp_se
2. Imposed for jitter performance.
3. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 â 0.2) x VIN_Vpp_se) / SR
4. This mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz that must be dc-coupled because they
have a duty cycle significantly less than 50%. A typical application example is a low-frequency video frame sync pulse.
Since the input thresholds (VIL, VIH) of this buffer are non-standard (0.33 and 0.49 V, respectively) refer to the input
attenuator circuit for dc-coupled pulsed LVCMOS in the Family Reference Manual at: www.silabs.com/
Support%20Documents/TechnicalDocs/Si5345-44-42-RM.pdf. Otherwise, for standard LVCMOS input clocks, use the
Standard Differential or Single-Ended ac-coupled input mode.
6
Rev. 1.0
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