SI5345-44-42 Datasheet, PDF (46/62 Pages) Silicon Laboratories – 10-CHANNEL

Si5345/44/42
Table 18. High-Level Register Map (Continued)
16-Bit Address
8-bit Page
Address
8-bit Register
Address Range
03
01
02–37
0C
17
22
2D
38
39–58
59–62
FE
04
87
05
0E - 14
15–1F
2A
2B
2C–35
36
38–39
3F
06–08
00–FF
09
01
1C
43
49
10–FF
00–FF
Content
Set Page Address
MultiSynth Divider (N0–N4) Settings
MultiSynth Divider (N0) Update Bit
MultiSynth Divider (N1) Update Bit
MultiSynth Divider (N2) Update Bit
MultiSynth Divider (N3) Update Bit
MultiSynth Divider (N4) Update Bit
FINC/FDEC Settings N0 - N4
Output Delay (t) Settings
Device Ready Status
Zero Delay Mode Set Up
Fast Lock Loop Bandwidth
Feedback Divider (M) Settings
Input Select Control
Fast Lock Control
Holdover Settings
Input Clock Switching Mode Select
Input Priority Settings
Holdover History Valid Data
Reserved
Set Page Address
Zero Delay Mode Settings
Control I/O Voltage Select
Input Settings
Reserved
46
Rev. 1.0