EFM8SB1 Datasheet, PDF (5/55 Pages) Silicon Laboratories – The EFM8SB1 highlighted features are listed below

EFM8SB1 Data Sheet
System Overview
3.2 Power
All internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devi-
ces without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the
device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when
not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little
power when they are not in use.
Table 3.1. Power Modes
Power Mode
Normal
Idle
Suspend
Stop
Sleep
Details
Core and all peripherals clocked and fully operational
• Core halted
• All peripherals clocked and fully operational
• Code resumes execution on wake event
• Core and digital peripherals halted
• Internal oscillators disabled
• Code resumes execution on wake event
• All internal power nets shut down
• Pins retain state
• Exit on any reset source
• Most internal power nets shut down
• Select circuits remain powered
• Pins retain state
• All RAM and SFRs retain state
• Code resumes execution on wake event
Mode Entry
—
Set IDLE bit in PCON0
Wake-Up Sources
—
Any interrupt
1. Switch SYSCLK to
HFOSC0 or LPOSC0
2. Set SUSPEND bit in
PMU0CF
• RTC0 Alarm Event
• RTC0 Fail Event
• CS0 Interrupt
• Port Match Event
• Comparator 0 Rising
Edge
Set STOP bit in PCON0 Any reset source
1. Disable unused ana-
log peripherals
2. Set SLEEP bit in
PMU0CF
• RTC0 Alarm Event
• RTC0 Fail Event
• Port Match Event
• Comparator 0 Rising
Edge
3.3 I/O
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P1.7 can be defined as gen-
eral-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an
analog function. Port pin P2.7 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P2.7.
• Up to 17 multi-functions I/O pins, supporting digital and analog functions.
• Flexible priority crossbar decoder for digital peripheral assignment.
• Two drive strength settings for each pin.
• Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1).
• Up to 16 direct-pin interrupt sources with shared interrupt vector (Port Match).
3.4 Clocking
The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system
clock comes up running from the 20 MHz low power oscillator divided by 8.
• Provides clock to core and peripherals.
• 20 MHz low power oscillator (LPOSC0), accurate to ±10% over supply and temperature corners.
• 24.5 MHz internal oscillator (HFOSC0), accurate to ±2% over supply and temperature corners.
• 16.4 kHz low-frequency oscillator (LFOSC0) or external RTC 32 kHz crystal.
• External RC, C, CMOS, and high-frequency crystal clock options (EXTCLK).
• Clock divider with eight settings for flexible clock scaling: Divide the selected clock source by 1, 2, 4, 8, 16, 32, 64, or 128.
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