EFM8SB1 Datasheet, PDF (20/55 Pages) Silicon Laboratories – The EFM8SB1 highlighted features are listed below

Parameter
Symbol Conditions
Min
Output Settling Time to 1/2 LSB
t_SETTLE
—
Startup Time
t_PWR
—
Note:
1. The PCA block may be used to improve IREF0 resolution by PWMing the two LSBs.
EFM8SB1 Data Sheet
Electrical Specifications
Typ
Max
Units
300
—
ns
1
—
µs
Table 4.14. Capacitive Sense (CS0)
Parameter
Symbol Conditions
Min
Typ
Max
Units
Single Conversion Time¹
t_CNV
12-bit Mode
13-bit Mode (default)
20
25
40
µs
21
27
42.5
µs
14-bit Mode
23
29
45
µs
16-bit Mode
26
33
50
µs
Number of Channels
N_CHAN
24-pin Packages
20-pin Packages
14
Channels
13
Channels
16-pin Packages
12
Channels
Capacitance per Code
C_LSB
Default Configuration, 16-bit codes
—
1
—
fF
Maximum External Capacitive
Load
C_EXTMAX
CS0CG = 111b (Default)
CS0CG = 000b
—
45
—
pF
—
500
—
pF
Maximum External Series Impe-
dance
R_EXTMAX CS0CG = 111b (Default)
—
50
—
kΩ
Note:
1. Conversion time is specified with the default configuration.
2. RMS Noise is equivalent to one standard deviation. Peak-to-peak noise encompasses ±3.3 standard deviations. The RMS noise
value is specified with the default configuration.
Table 4.15. Port I/O
Parameter
Output High Voltage (High Drive)
Output Low Voltage (High Drive)
Output High Voltage (Low Drive)
Output Low Voltage (Low Drive)
Input High Voltage
Input Low Voltage
Symbol
V_OH
V_OL
V_OH
V_OL
V_IH
V_IL
Test Condition
I_OH = –3 mA
I_OL = 8.5 mA
I_OH = –1 mA
I_OL = 1.4 mA
V_DD = 2.0 to 3.6 V
V_DD = 1.8 to 2.0 V
V_DD = 2.0 to 3.6 V
V_DD = 1.8 to 2.0 V
Min
Typ
Max
Unit
V_DD – 0.7
—
—
V
—
—
0.6
V
V_DD – 0.7
—
—
V
—
—
0.6
V
V_DD – 0.6
—
—
V
0.7 x V_DD
—
—
V
—
—
0.6
V
—
—
0.3 x V_DD
V
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