EFM8SB1 Datasheet, PDF (14/55 Pages) Silicon Laboratories – The EFM8SB1 highlighted features are listed below

EFM8SB1 Data Sheet
Electrical Specifications
Parameter
Symbol Conditions
Min
Typ
Max
Units
Programmable Current Reference I_IREF0
(IREF0) Supply Current¹⁰
Current Source, Either Power
Mode, Any Output Code
—
10
—
µA
Low Power Mode, Current Sink
—
1
—
µA
IREF0DAT = 000001
Low Power Mode, Current Sink
—
11
—
µA
IREF0DAT = 111111
High Current Mode, Current Sink
—
12
—
µA
IREF0DAT = 000001
High Current Mode, Current Sink
—
81
—
µA
IREF0DAT = 111111
Note:
1. Based on device characterization data; Not production tested.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Digital Supply Current depends upon the particular code being executed. The values in this table are obtained with the CPU exe-
cuting an “sjmp $” loop, which is the compiled form of a while(1) loop in C. One iteration requires 3 CPU clock cycles, and the
flash memory is read on each cycle. The supply current will vary slightly based on the physical location of the sjmp instruction and
the number of flash address lines that toggle as a result. In the worst case, current can increase by up to 30% if the sjmp loop
straddles a 64-byte flash address boundary (e.g., 0x007F to 0x0080). Real-world code with larger loops and longer linear sequen-
ces will have few transitions across the 64-byte address boundaries.
4. Includes supply current from regulator and oscillator source (24.5 MHz high-frequency oscillator, 20 MHz low-power oscillator, 1
MHz external oscillator, or 32.768 kHz RTC oscillator).
5. IDD can be estimated for frequencies < 14 MHz by simply multiplying the frequency of interest by the frequency sensitivity num-
ber for that range, then adding an offset of 84 µA. When using these numbers to estimate I_DD for > 14 MHz, the estimate should
be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: V_DD = 3.0 V;
F = 20 MHz, I_DD = 3.6 mA – (25 MHz – 20 MHz) x 0.088 mA/MHz = 3.16 mA assuming the same oscillator setting.
6. Idle IDD can be estimated by taking the current at 25 MHz minus the difference in current indicated by the frequency sensitivity
number. For example: V_DD = 3.0 V; F = 5 MHz, Idle I_DD = 1.75 mA – (25 MHz – 5 MHz) x 0.067 mA/MHz = 0.41 mA.
7. ADC0 always-on power excludes internal reference supply current.
8. The internal reference is enabled as-needed when operating the ADC in burst mode to save power.
9. Includes only current from regulator, CS module, and MCU in suspend mode.
10. IREF0 supply current only. Does not include current sourced or sunk from IREF0 output pin.
Table 4.3. Reset and Supply Monitor
Parameter
Symbol
VDD Supply Monitor Threshold
V_VDDM
V_WARN
VDD Supply Monitor Turn-On Time t_MON
Power-On Reset (POR) Monitor
Threshold
V_POR
V_DD Ramp Time
Reset Delay
t_RMP
t_RST
RST Low Time to Generate Reset t_RSTL
Test Condition
Reset Trigger
Early Warning
Rising Voltage on V_DD
Falling Voltage on V_DD
Time to V_DD ≥ 1.8 V
Time between release of reset
source and code execution
Min
Typ
Max
Unit
1.7
1.75
1.8
V
1.8
1.85
1.9
V
—
300
—
ns
—
1.75
—
V
0.45
0.7
1.0
V
—
—
3
ms
—
10
—
µs
15
—
—
µs
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