EFM8SB1 Datasheet, PDF (4/55 Pages) Silicon Laboratories – The EFM8SB1 highlighted features are listed below

3. System Overview
3.1 Introduction
EFM8SB1 Data Sheet
System Overview
C2CK/RSTb
VDD
GND
Power On
Reset/PMU
Wake
Reset
Debug /
Programming
Hardware
CIP-51 8051 Controller
Core
8/4/2 KB ISP Flash
Program Memory
256 Byte SRAM
256 Byte XRAM
C2D
VREG
Digital
Power
SYSCLK
System Clock
Configuration
XTAL1
XTAL2
Precision
24.5 MHz
Oscillator
Low Power
20 MHz
Oscillator
External
Oscillator
Circuit
XTAL3
XTAL4
RTC
Oscillator
SFR
Bus
Port I/O Configuration
Digital Peripherals
UART
Timers 0,
1, 2, 3
PCA/WDT
SMBus
SPI
CRC
Priority
Crossbar
Decoder
Crossbar Control
Port 0
Drivers
Port 1
Drivers
Port 2
Driver
Analog Peripherals
6-bit
IREF
Internal External
VREF VREF
12-bit
ADC
IREF0
VDD
VREF
Temp
Sensor
14-Channel
Capacitance
To Digital
Converter
GND
+
-
Comparator
P0.n
P1.n
P2.n
Figure 3.1. Detailed EFM8SB1 Block Diagram
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.2 | 3