S5H1420 Datasheet, PDF (9/31 Pages) Samsung semiconductor – Channel Decoder for DVB-S/DSS

S5H1420
DBS Channel Decoder for DVB-S/DSS
■1/2, 2/3, 3/4, 5/6, 7/8 for DVB-S
■1/2, 2/3, 6/7 for DSS
For each enabled rate, the current error rate is compared to a programmable threshold.
If it is greater than this threshold, another phase (or another rate) is tried until the right rate is obtained.
A programmable hysterics is added to avoid losing the phase during short-term perturbation. The rate
may also be imposed by external software, and the phase is incremented only upon request by the
microprocessor. The error rate may be read at any time in order to use an algorithm other than that
implemented.
The Viterbi decoder produces an absolute decoding. The decoder is controlled via several Viterbi
Threshold Registers (Registers 29, 2A, 2B, 2C, 2D and 2E). For each Viterbi Threshold Register, bits 7
to 0 represent a normalization rate threshold – the average number of normalization occurring during
sync periods. The sync period is controlled via Viterbi Sync Register (Register 2F). The puncture Rate
and Viterbi initial configuration is in Address 30, 31. The automatic rate research is only done through
the enabled rates (see the corresponding bit set in the Puncture register). In DSS, it is recommended
that you disable puncture rates 3/4, 5/6 and 7/8 in order to save time in the synchronization process.
The Viterbi decoder sync search can control using the Puncture register.
3.4.4 Synchronization
In DVB-S, the packet length after inner decoding is 204. The sync word is the first byte of each packet.
Its value is Hex 47, but this value is complemented every 8 packets. In DSS, the packet length is 147
and the sync word is Hex 1D.
An Up/Down Sync counter counts whenever a sync word is recognized with the correct timing and
counts down during each missing sync word.
This counter is bounded by a programmable maximum - when this value is reached, the SYNC_FLAG
bit (“locked”) is set in the SYNC02 register. When the event counter counts down to until 0, this flag is
reset.
3.4.5 Error monitoring
A 16-bit counter, ERRCNT, allows the counting of errors at different levels. ERRCNT is fed either by:
■ the input QPSK bit errors (that are corrected by the Viterbi decoder), or,
■ the bit, or,
■ the byte error (it will be corrected by the Reed-Solomon decoder)
■ the packet error (It is uncorrectable and lead to a pulse at the ERROR output)
The content of ERRCNT may be transferred to the read only registers ERR_CNT_L (LSB) and ERR-
CNT_H (MSB). Two functional modes are proposed, depending on a control register bit:
1. ERR_DISP = 0. The uncorrectable block flag ERROR that error count is not incremented.
2. ERR_DISP = 1. The uncorrectable block flag ERROR that error is counted as 27 erroneous bits
(It has nine erroneous bytes with three corrupted bits per byte).
3.4.6 Convolutional deinterleaver
× In DVB-S, the Convolutional deinterleaver is 17 12. The periodicity of 204 bytes per sync byte is
× retained. In DSS, the Convolutional deinterleaver is 146 13, and there is also a periodicity of 147
bytes per sync byte. The deinterleaver may be bypassed.
3.4.7 Reed-Solomon decoder and descrambler
The input blocks are 204-byte long with 16 parity bytes in DVB-S. The sync byte is the first byte of the
block. Up to 8 byte errors may be fixed.
The code generator polynomial is:
g( χ ) = ( χ − α ⁰) ( χ − α ¹) (...) ( χ − α ¹⁵)
Over the Galois Field generated by:
α ⁸ + α ⁴ + α ³ + α ² + 1=0
Energy dispersal descrambler and output energy dispersal descrambler generator:
χ ¹⁵ + χ ¹⁴ + 1
The polynomial is initialized every eight blocks with the sequence 100101010000000.
The sync words are unscrambled and the scrambler is reset every 8 packets.
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