S5H1420 Datasheet, PDF (19/31 Pages) Samsung semiconductor – Channel Decoder for DVB-S/DSS

S5H1420
DBS Channel Decoder for DVB-S/DSS
Loop filter control registers (Address: 0x09 – 0x0D)
Addr.
RegName
(Reset val)
Signal name
WT_TNCO
WT_PNCO
0x09
Loop01
(0x30)












Width Property Description
Write TNCO center frequency
[7] R/W _{[0 and then 1] The write operation enabled, when user set}
WT_TNCO “0” and then “1”
Write PNCO center frequency
[6] R/W _{[0 and then 1] The write operation enabled, when user set}
WT_PNCO “0” and then “1”
[5] R/W Set to “1”
[4] R/W Set to “1”
[3] R/W Set to “0”
[2] R/W Set to “0”
[1] R/W Set to “0”
[0] R/W Set to “0”
LOOP_OUT
Loop filter monitoring selection
[7] R/W _{[1] Loop filter accumulator + NCO}
0x0A
Loop02
(0x65)
KICK_VAL
KICK_MUL
0x0B
Loop03
(0x78)
PGA_PLF
IGA_PLF
0x0C
Loop04
(0x28)
PGT_PLF
IGT_PLF
[6:4]
[3:0]
[3:0]
[7:4]
[3:0]
[7:4]
R/W
R/W
R/W
R/W
R/W
R/W
[0] Loop filter accumulator
The value that gets injected into the accumulator when a “kick” is
needed.
The number of bits KICK_VAL is up-shifted (2^N) before it is
injected into the accumulator.
Phase loop, proportional gain (2^PGA_PLF) in the acquisition mode
(default +8 added)
Phase loop, integral gain (2^IGA_PLF) in the acquisition mode
Phase loop, proportional gain in the tracking mode
(default +8 added)
Integral gain in the tracking mode
0x0D
Loop05
(0x17)
PG_TLF
IG_TLF
[3:0] R/W Timing loop, proportional gain (default +8 added)
[7:4] R/W Timing loop, integral gain
NCO control registers (Address: 0x0E – 0x13)
Addr.
RegName
(Reset val)
Signal name
0x0E
Pnco01
(0x00)
PNCO1 [31:24]
Width Property Description
LOOP_OUT [1]
[7:0] R/W
Read PLF accumulator + PNCO
0x0F
Pnco02
(0x00)
PNCO2 [23:16]
[7:0]
LOOP_OUT [0]
R/W
Read PLF accumulator
0x10
Pnco03
(0x00)
PNCO3 [15:08]
[7:0]


R/W


0x11
Tnco01
(0x00)
TNCO1 [31:24]
[7:0]
LOOP_OUT [1]
R/W
Read TLF accumulator + TNCO
0x12
Tnco02
(0x00)
TNCO2 [23:16]
[7:0]
LOOP_OUT [0]
R/W
Read TLF accumulator
0x13
Tnco03
(0x00)
TNCO3 [15:08]
[7:0]


R/W


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