S5H1420 Datasheet, PDF (8/31 Pages) Samsung semiconductor – Channel Decoder for DVB-S/DSS

S5H1420
DBS Channel Decoder for DVB-S/DSS
The carrier lock detector operates the same as the timing lock detector in the Phase locked loop (PLL).
User can monitor the MSB 8 bits of PLL lock counter in Address 0x19 and the PLL lock flag in Address
0x14.
3.3.3 Derotator frequency
The derotator frequency can be either measured (read operation) or forced (write operation).
f_derot ⁼
f sym
×
24
2
f clk
3.3.4 Automatic frequency detector
The automatic frequency detector (AFD) can evaluate the carrier frequency offset quickly, and may be
coupled to the carrier recovery loop.
The digital loop filter of PLL has two paths, proportional and integral, with programmable gain
respectively. The integral path contains an accumulator whose contents can be analyzed as a
averaged carrier frequency offset.
The phase error signal goes into two paths, the respective gains are applied, the “I” path is integrated,
and the two are added together. A Kicker of AFD can help PLL to achieve lock fast. The Kicker finds
the phase error signal for large transitions, inserts a large value, into the “I” path. Therefore, PLL can
trace the large frequency offset.
3.3.5 False lock
A false lock occurs when phase lock has been detected in the QPSK, but the correct central frequency
has not yet been reached. This situation occurs in QPSK for frequency offset points that are multiples
of f_sym /4, where f_sym is the QPSK symbol rate, and also at other offsets dictated by the discrete nature
of the carrier recovery loop. Therefore, the carrier recovery loop must be handled to take care of a
false lock condition.
3.4 Forward Error Correction
3.4.1 FEC modes
Since the S5H1420 is a multi-standard decoder, several combinations are possible, at different levels:
■ the demodulator may accept either QPSK or BPSK signals - the only impact is on the carrier
algorithm choice. The algorithm choice also affects the carrier lock detector and the noise evaluation.
■ there are two primary options concerning the FEC operation - between DVB-S, DSS and Reserved
Mode.
■ there are two options concerning the FEC feeding. The first is IQ flow, which is the usual case in
QPSK modes DVB-S or DSS. The second mode is I-only flow, used for BPSK.
The FEC Mode Register is in Address Hex 22.
In Modes DVB-S and DSS, data is fed to the Soft Decisions.
3.4.2 Soft decisions
The adaptive equalizer output is converted into 4-bit sign-magnitude format by the soft decision block,
for use by the Viterbi decoder. The MSB corresponds to the sliced bit value. The 3 LSBs of the soft
decisions represent the confidence of the sliced bit value, where 111 are high confidence, and 000 is
low confidence. A programmable set of thresholds can be used in generating the three LSBs and,
consequently, in optimizing the Viterbi decoder performance as a function of code rate.
3.4.3 Viterbi decoder and synchronization
The convolutional codes are generated by the polynomial G_x = 171 octets and G_y = 133 octets in
modes DVB-S or DSS. The Viterbi decoder computes for each symbol the metrics of the four possible
paths, proportional to the square of the Euclidian distance between the received I and Q and the
theoretical symbol value.
The puncture rate and phase are estimated on the error rate basis. Several rates are allowed and may
be enabled/disabled through register programming:
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