S5H1420 Datasheet, PDF (3/31 Pages) Samsung semiconductor – Channel Decoder for DVB-S/DSS

1. INTRODUCTION
S5H1420
DBS Channel Decoder for DVB-S/DSS
1.1 Overview
The S5H1420 is a single chip channel decoder IC for DBS (Digital Broadcasting System for Satellite)
receiver. It consists of a multi-standard QPSK/BPSK demodulator and FEC (Forward Error Correction)
decoder compliant with DVB-S and DSS standard. For multi-antenna control it provides DiSEqC1.x
and 2.0 standards.
1.2 Features
■ Compliant to DVB-S and DSS standard.
■ Single chip decoder (ADC/QPSK/FEC).
■ Flexible Interface (I²C, MPEG2).
■ DiSEqC 1.x or 2.0 specification support.
■ Satellite dish control.
■ DC offset cancellation.
■ Automatic gain control
■ Nyquist filter: 0.35 for DVB-S, 0.2 for DSS.
■ Fully digital synchronization.
Symbol timing recovery range up to ± 50000 ppm.
Carrier recovery range up to ±12.5% of symbol rate.
■ Carrier offset cancellation up to ±1/2sampling frequency
■ Modulation rate from 1 to 87Mbps(1 ~ 50 Msps)
■ QPSK demodulation quality estimation
■ Viterbi decoding quality estimation.
Viterbi Input and output BER measurement.
Support depuncturing code rate from 1/2 to 7/8.
■ Convolutional deinterleaver and Reed-Solomon decoder
■ Automatic byte and frame synchronization
■ Automatic spectral inversion ambiguity resolution.
■ I²C repeater for RF part
■ Power down control
■ Low power CMOS technology
■ 3.3V Single power using diode for 2.5V
■ Compact size package: 64LQFP-1010
1.3 Applications
DVB-S Receiver and STB
Digital satellite TV
PCI satellite Card
1.4 Ordering information
Type Number
1. S5H1420X01
Package
64 LQFP-1010
Description
Plastic Low Profile Quad Flat Package;
64 leads (lead length 1.0mm)
Body 10x10x1.0 mm
Samsung Electronics Co, Ltd. Proprietary Information
-3 -