S5H1420 Datasheet, PDF (17/31 Pages) Samsung semiconductor – Channel Decoder for DVB-S/DSS

ID control register (Address: 0x00)
Addr.
RegName
(Reset val)
Signal name
Width Property Description
0x00
ID01
(0x03)
S5H1420_ID
[7:0]
R Revision ID
S5H1420
DBS Channel Decoder for DVB-S/DSS
System control registers (Address: 0x01-0x02)
Addr.
RegName
(Reset val)
Signal name


Width Property Description
[4] R/W Set to “0”
0x01
CON_0
(0x00)
SOFT_RST




System soft reset mode (active high)
[3] R/W
[1] Enable [0] Disable
[2] R/W Set to “0”
[1] R/W Set to “0”
DSS_ DVB
DSS/DVB mode selection
[0] R/W
[1] DSS [0] DVB


[6] R/W Set to “0”


[5] R/W Set to “0”
SER_SEL
[4] R/W Set to “1”


[3] R/W Set to “0”


[2] R/W Set to “0”
Power down mode
0x02
CON_1
(0x00)
PWR_DN
[1] R/W [1] Power down enable
[0] Power down disable
I2C repeater control
[1] I2C repeater enable,
I2C_RPT
[0] I2C repeater disable.
[0] R/W
Note: The master should be set this bit to “1” in order to interface
with the tuner.
When the master is not communicated with the tuner, this bit
should be set to “0”
PLL control registers (Address: 0x03-0x04)
Addr. RegName Signal name
Width Property Description
0x03
0x04
PLL01
(0x50)
M
PLL02 ^P
(0x40) _S
[7:0]
[5:0]
[7:6]
R/W
R/W
R/W
PLL programming information
F_out = ((M+8)ƒF_in)/((P+2)×2^s)
F_in = 4 MHz


Samsung Electronics Co, Ltd. Proprietary Information
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