S5H1420 Datasheet, PDF (12/31 Pages) Samsung semiconductor – Channel Decoder for DVB-S/DSS

3.4.9.3 MPEG Clock Control
S5H1420
DBS Channel Decoder for DVB-S/DSS
- Through Register Setting, S5H1420 can control MPEG CLOCK to MCU.
STB MCU
Symbol Rate
S5H1420 Master
Clock
Sampling
60MHz
Symbol Rate Symbol Rate
>= 25
< 25
59MHz
88MHz
1
2
81MHz
Symbol Rate Symbol Rate
>= 25
< 25
80MHz
88MHz
1
2
- Control register, 3-bit, uses Address 0x22 (MPEG_CLK_INTL [2:0])
- If Control registers changes, Some blocks will be reset automatically.
- In case, Auto reset does not work, these blocks’ reset can be done manually.
- MPEC IF Clock is made by Control Register and the Rules are as follows
- Tmp = (fMCLK/fSR)*(1/(2*CR)), fMCLK : System Clock Frequency,fSR : Symbol Rate, CR : Code
Rate
Control
Register
(0x22)
0
1
2
3
4
5
6
7
MPEG
MPEG Clock
Clock(Parallel)
(Serial)
Range
Divide
F_MCLK/8
F_MCLK/16
F_MCLK/32
F_MCLK/64
F_MCLK/96
F_MCLK/128
F_MCLK/192
F_MCLK/256
F_MCLK
1<Tmp≤2
1
F_MCLK/2
2<Tmp≤5
2
F_MCLK/4
5<Tmp≤9
3
F_MCLK/8
9<Tmp≤13
4
F_MCLK/12
13<Tmp≤17
5
F_MCLK/16
17<Tmp≤25
6
F_MCLK/24
25<Tmp≤33
7
F_MCLK/32
33<Tmp
8
MCLK=88 MHz
MPEG Clock (MHz)
Serial
88
44
22
11
7.3333
5.5
3.6666
2.75
Parallel
11
5.5
2.75
1.375
0.9166625
0.6875
0.458325
0.34375
Example1) System Clock Frequency = 88MHZ, Symbol Rate : 44MSps
Code Rate
1/2
2/3
3/4
5/6
6/7
7/8
Tmp Value
2
1.5
1.333
1.2
1.166
1.142
Setting Control Register Value
1
0
0
0
0
0
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