S5H1420 Datasheet, PDF (13/31 Pages) Samsung semiconductor – Channel Decoder for DVB-S/DSS

S5H1420
DBS Channel Decoder for DVB-S/DSS
3.5 Front end interfaces
3.5.1 I²C interface
The standard I²C protocol is used whereby the first byte is Hex A0 for a write operation, or Hex A1 for a
read operation.
3.5.2 Write operation
The byte sequence is as follows:
■ the first byte gives the device Address plus the direction bit (R/W = 0).
■ the second byte contains the internal Address of the first register to be accessed.
■ the next byte is written in the internal register. Following bytes (if any) are written in successive
internal registers.
■ the transfer lasts until stop conditions are encountered.
■ the S5H1420 acknowledges every byte transfer.
3.5.3 Read operation
The Address of the first register to read is programmed in a write operation without data, and
terminated by the stop condition. Then, another start is followed by the device Address and R/W= 1. All
following bytes are now data to be read at successive positions starting from the initial Address. Figure
2 shows the I²C Normal Mode Write and Read Registers.
Figure 2: I²C Read and Write operations in Mode
Write register 0 to 3 with AA, BB, CC, and DD
%FWJDF
3FHJTUFS
4UBSU "EESFTT "$, "EESFTT "$, %BUB"" "$, %BUB## "$, %BUB$$ "$, %BUB%% "$, 4UPQ
8SJUF
%

Read register 2 and 3
4UBSU %FWJDF
"EESFTT
8SJUF
% "$, 3FHJTUFS
"EESFTT
 "$, 4UPQ
4UBSU
%FWJDF
"EESFTT
3FBE
%
"$, %BUB
3FBE
$$ ^"$, %BUB
3FBE
%% ^{"$, 4UPQ}
3.5.4 Identification register
The Identification Register (at Address Hex 00) gives the release number of the circuit.
The content of this register at reset is presently (Hex02)
3.5.5 Sampling frequency
The S5H1420 converts the analog inputs into digital 6 bit I and Q flow. The sampling frequency is f_clk
which is derived from an external reference described in Section 3.5.6 ‘Clock generation’. The
maximum value of fclk is 90 MHz.
The sampling causes the repetition of the input spectrum at each integer multiple of f_clk One has to
ensure that no frequency component is folded in the useful signal bandwidth of f_sym (1+ α)/2 where f_sym
is the symbol frequency, and α is the roll-off value.
3.5.6 Clock generation
An integrated PLL is the circuit synchronizing an output signal (generated by a VCO with a reference
signal in frequency as well as in phase. In this application, it includes the following basic blocks. The
phase frequency detector to detect the phase difference between the reference frequency and the
output frequency (after division) and to control the charge pumps voltage. Register setting can program
the desired frequency.
× × f_out = (m f_in)/ (p s)
f_in: input frequency, m=M+8, p=P+2, s=2^S
M: Register 03, P: Register 04 [5:0], S: Register 04[7:6]
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