S5H1420 Datasheet, PDF (23/31 Pages) Samsung semiconductor – Channel Decoder for DVB-S/DSS

S5H1420
DBS Channel Decoder for DVB-S/DSS
MPEG control registers (Address: 0x38~0x39)
Addr.
RegName
(Reset val)
Signal name
Width Property Description
ERR_POL
Packet error polarity
[3] R/W
[1] Active low [0] Active high
SYNC_POL
0x38
Mpeg01
(0x00)
VALID_POL
Sync polarity
[2] R/W
[1] Active low [0] Active high
Data valid polarity
[1] R/W
[1] Active low [0] Active high
CDCLK polarity
CDCLK_POL
[0] R/W [1] Falling edge event
[0] Rising edge event


[6] R/W Set to “1”


[5] R/W Set to “1”


[4] R/W Set to “1”
0x39
Mpeg02
(0x3D)
CLK_CONT


Clock continuous mode
[3]
R/W _{[1] Continuous clock, [0] Clock is enable during payload data}
transfer
[2] R/W Set to “1”
SER_PAR
Serial / Parallel mode
[1] R/W
[1] Serial mode, [0] Parallel mode
DSS_SYNC
DSS sync mode
[0] R/W
[1] Output sync, [0] No output sync
DiSEqC control registers (Address: 0x3A~ 0x3C)
Addr.
RegName
(Reset val)
Signal name
Width Property Description
0x3A
DiS01
(0x01)
TONE_FREQ
[7:0]
R/W
Tone frequency ratio
*Note: f_tone = f_clk / (TONE_FREQ ×32)
RCV_EN
DiSEqC receive enable mode
[7] R/W
[1] Receive enable [0] Receive disable
DIS_LENGTH [6:4] R/W Message length
Data Transfer ready / finish
DIS_RDY
0x3B
DiS02
(0x00)
SWICH_CON
[1] Ready [0] Finish
[3] R/W
*Note: The Microprocessor set to “1” only when this bit is “0”.
When this bit is “1”, the slaver is not yet received message. The
slaver is starting to receive the signal at the rising edge detection
Satellite switch in tone burst mode
[2] R/W
[1] Satellite B [0] Satellite A
LNB control mode
[0] Continuous mode
LNB_CON
[1:0] R/W [1] Tone burst mode
[2] DiSEqC mode
[3] Reserved
Samsung Electronics Co, Ltd. Proprietary Information
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