S5H1420 Datasheet, PDF (14/31 Pages) Samsung semiconductor – Channel Decoder for DVB-S/DSS

S5H1420
DBS Channel Decoder for DVB-S/DSS
3.5.7 I²C bus repeater
In low symbol rate applications, signal pollution generated by the SDA/SCL lines of the I²C bus may
dramatically worsen tuner phase noise. In order to avoid this problem, the S5H1420 offers an I2C bus
repeater so that the RFSDA and RFSCL are active only when necessary. Both RFSDA and RFSCL
pins are set high at reset. When the microprocessor writes a 1 into register bit I2C_RPT, the next I²C
message on SDA and SCL is repeated on the RFSDA and RFSCL pins respectively, until stop
conditions are detected.
To write to the tuner, the external microprocessor must, for each tuner message, perform the following:
■ Program 1 in I2C_RPT.
■ Send the message to the tuner.
Any size of byte transfers is allowed, regardless of the Address, until the stop conditions are detected.
Transfers are fully bi-directional. The I2C_RPT bit is automatically reset at the stop condition. The I²C
repeater register in Address Hex 02 controls configuration.
3.5.9 DiSEqC interface
This interface allows for the simplification of real time processing of the dialog from microprocessor to
LNB. It includes register set (8 bytes) that is filled by the microprocessor via the I²C bus, and then
transmitted by modulating to 22 kHz clock. The S5H1420 support DiSEqC2.0 for bi-directional interface
between microprocessor to LNB and can change the tone frequency by register setting.
< Transmission >
The S5H1420 have three modes for DiSEqC Interface.
■ Continuous Mode: The S5H1420 generates continuous tone signal until the mode changes.
■ Tone Burst Mode: For the “Modulated Tone Burst”, only one byte (with value Hex FF) and parity bit 1
is sent. As a result, the output signal is 9 bursts of 0.5ms, separated by 8 intervals of 1ms.
For the “Unmodulated Tone Burst” only one byte (with value Hex 00) is sent. The parity bit is still 1, and
as a result, the signal is a continuous train of 12.5ms.
■ DiSEqC Mode: DiSEqC is a command-based protocol used to control multiple LNBs in a cascaded
network configuration. The S5H1420 complies with DiSEqC2.0. Figure illustrates a typical application
of the DiSEqC mode.
< Receive >
The S5H1420 receives the data from LNBs using DiSEqC pin. In order to receive the data from LNBs
should set the register RCV_EN to 1. The received data is stored to register set.
Two control signals are available on the I²C bus:
DiS_RDY (Transfer Ready/Finish) and DiS_LENGTH (Message Length).
A typical byte transfer loop, as seen from the microprocessor, may be the following:
While (there is data to transfer)
1 Read the DiS_RDY signals
2 If DiS_RDY =0, Write byte to transfer in the register set.
3 Set the DiS_LENGTH.
4 Set the DiS_RDY =1.
Note, for the above transfer loop, the following:
■ At the beginning, the register set is empty (DiS_RDY =0). This is the idle state.
■ As soon as set the DiS_RDY =1, the transfer will begin.
■ After the last transmitted byte, the interface will go into the idle state.
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