S5H1420 Datasheet, PDF (20/31 Pages) Samsung semiconductor – Channel Decoder for DVB-S/DSS

S5H1420
DBS Channel Decoder for DVB-S/DSS
QPSK monitoring registers (Address: 0x14 – 0x1F)
Addr.
RegName
(Reset val)
Signal name
Width Property Description


[7:4] R Reserved


0x14
Monitor01
(0x00)
TLOCK
PLOCK
0x15
Monitor02
(0x00)
PRE_LEVEL
[3:2]
R Reserved
Timing loop lock (Symbol sync)
[1]
R [1] Timing loop has locked
[0] Timing loop has not locked
Phase loop lock (Carrier sync)
[0]
R [1] Phase loop has locked
[0] Phase loop has not locked
[7:0] R PRE-AGC gain level
0x16
Monitor03
(0x00)
POST_LEVEL
[7:0]
R POST-AGC gain level
0x17
Monitor04
(0x00)
DC_I_LEVEL
[7:0] R DC offset of I samples
0x18
Monitor05
(0x00)
DC_Q_LEVEL
[7:0]
R DC offset of Q samples
0x19
Monitor06
(0x00)


[7:0] R Reserved
0x1A
Monitor07
(0x00)


[7:0]




(0x1B ~ 0x1E)




[7]
0x1F
Monitor12
(0x00)
QPSK_OUT
[6:1]
DC_FREEZE
[0]




(0x20 ~ 0x21)


R Reserved

Reserved

Reserved
R QPSK output monitoring
R/W [1] Do not update DC_OFFSET

Reserved
Samsung Electronics Co, Ltd. Proprietary Information
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