S5H1420 Datasheet, PDF (18/31 Pages) Samsung semiconductor – Channel Decoder for DVB-S/DSS

S5H1420
DBS Channel Decoder for DVB-S/DSS
QPSK control registers (Address: 0x05 – 0x06)
Addr.
RegName
(Reset val)
Signal name
Width Property Description
KICK_EN
[7] R/W [1] PLL Kicker enable [0] Disable




DC_EN
0x05
QPSK01
(0xBC)




MODE
Q_START






0x06
QPSK02
(0xC1)


DUMP_ACC
DC_WIN
[6] R/W Set to “0”
[5] R/W Set to “1”
DC offset remove
[4] R/W
[1] Enable [0] Disable
[3] R/W Set to “1”
[2] R/W Set to “1”
QPSK operation mode
[1] R/W [1] 1 sampling/1 symbol
[0] 2 sampling/1 symbol
QPSK start signal
[0] R/W
[1] Start [0] Idle
[7] R/W Set to “1”
[6] R/W Set to “1”
[5] R/W Set to “0”
[4] R/W Set to “0”
Dump phase loop filter & timing loop
[3]
R/W ^{filter accumulator}
[0 and then 1] The read operation enabled, when user set
DUMP_ACC “0” and then “1”.
[2:0]
R/W
Window position from MSB removing DC offset. Unsigned integer
(0 † DC_WIN† 7)
AGC control registers (Address: 0x07 – 0x08)
Addr.
RegName
(Reset val)
Signal name
Width Property Description
INV_PULSE
PWM signal is reversed
[7]
R/W _{[1] PWM signal active low}
0x07
Pre01
(0x30)


[0] PWM signal active high
[6] R/W Set to “0”


[5] R/W Set to “1”
PRE_TH
[4:0] R/W PRE-AGC threshold
0x08
Post01
(0x10)


POST_TH
[7:6] R/W Set to “0”
[5:0] R/W POST-AGC threshold
Samsung Electronics Co, Ltd. Proprietary Information
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