S5H1420 Datasheet, PDF (6/31 Pages) Samsung semiconductor – Channel Decoder for DVB-S/DSS

3. FUNCTIONAL DESCRIPTION
S5H1420
DBS Channel Decoder for DVB-S/DSS
3.1 Signal processing
3.1.1 I and Q inputs
The dual ADC can get differential (IP/IN, QP/QN) or single inputs (IP, QP), I/Q signals from the tuner
are fed to the IP and QP inputs through a DC coupling capacitor and IN and QN must be set DC
voltage as CML (typical: 1/2VDD). The reference voltage of high [VREF-H] and low [VREF-L] should
be supplied from external generator for application flexibility.
3.1.2 PRE-AGC
The power of I/Q signal is compared to a programmable threshold value, and the difference is
integrated. This signal is then converted into a Pulse Width Modulation (PWM) signal to drive the AGC
output and it will be low pass filtered by a simple RC analog filter to control the gain command of any
amplifier before the A/D converter. The PWM output operates at f_clk/ (1, 4, 8 and 16) in order to
decrease the radiated noise and to simplify the filter design, and is a 5 V tolerant open drain stage.
The PRE-AGC Controls are in Address 0x07 and the PRE-AGC integrator register is in Address 0x15.
3.1.3 Root raised cosine and rate conversion filter
The Root raised cosine (RRC) and rate conversion filter performs anti-aliasing filtering, root raised
cosine shaping, rate conversion, timing synchronization and tracking with the timing loop.
Two roll-off factors are available: 0.35 (DVB-S) and 0.20 (DSS).
3.1.4 Offset cancellation
This device suppresses the residual I/Q DC component in the QPSK system control register in
Addresses 0x05 and 0x06.
3.1.5 POST-AGC
The POST-AGC shall be able to adjust the gain of the incoming I/Q sample from the RRC and rate
conversion filter and implement the closed loop that sets the gain adjustment. The reset value (0x8000)
of the POST-AGC integrator register can allow an initial settling time of less than 50k master clock
periods.
The POST-AGC Controls are in Address 0x08 and the POST-AGC integrator register is in Address
0x16.
3.2 Timing recovery
3.2.1 Timing control
The timing loop is programmed with the expected symbol frequency.
We have δ parameter, which determine one or two sampling method. It can be expressed as:
In contrast,
(1+ α)^ĕ fsym > ^{f clk} for δ =1.
2
(1+ α)^ĕ fsym < ^{f clk} for δ =2.
2
Where α is roll-off factor: 0.35 for DVB-S, 0.2 for DSS.
Thus
Timing NCO frequency word register setting is:
NCO frequency word = ^{f sym ĕ}2^24ĕ δ
f clk
Samsung Electronics Co, Ltd. Proprietary Information
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