S5H1420 Datasheet, PDF (21/31 Pages) Samsung semiconductor – Channel Decoder for DVB-S/DSS

S5H1420
DBS Channel Decoder for DVB-S/DSS
FEC control registers (Address: 0x22)
Addr.
RegName
(Reset val)
Signal name


Width Property Description
[6] R/W Set to “0”


[5] R/W Set to “0”


[4] R/W Set to “0”


[3] R/W Set to “0”
Tmp=(FMClk/FSR)ƒ(1/(2ƒCR))
0x22
FEC01
(0x01)
FMClk: System Clock Frequency
FSR: Symbol Rate, CR: Code Rate
MPEG_CLK_INTL [2:0]


R/W
0: 1<Tmp† 2
4: 13<Tmp† 17
1: 2<Tmp† 5 5: 17<Tmp† 25
2: 5<Tmp† 9 6: 25<Tmp† 33
3: 9<Tmp† 13 7: 33<Tmp
Viterbi control registers (Address: 0x30 – 0x31)
Addr.
RegName
(Reset val)
Signal name




Width Property Description
[7] R/W Set to “0”
[6] R/W Set to “0”
VIT_SR78
[1] Include code rate 7/8 in sync search
[5] R/W
[0] Disable
VIT_SR67
[1] Include code rate 6/7 in sync search
[4] R/W
[0] Disable
0x30
Vit08
(0xFF)
VIT_SR56
[1] Include code rate 5/6 in sync search
[3] R/W
[0] Disable
VIT_SR34
[1] Include code rate 3/4 in sync search
[2] R/W
[0] Disable
VIT_SR23
[1] Include code rate 2/3 in sync search
[1] R/W
[0] Disable
VIT_SR12
[1] Include code rate 1/2 in sync search
[0] R/W
[0] Disable
Parameter fix mode
PARM_FIX
[4] R/W [1] Known parameter
[0] Unknown parameter
0x31
VIT9
(0x00)
VIT_INV_SPEC
[3]
Initial spectrum information
R/W
[1] Inv spectrum [0] Not inv spectrum
Start synchronization search at code rate as follows:
VIT_FR
[0] R=1/2 [1] R=2/3
[2:0] R/W
[2] R=3/4 [3] R=5/6
[4] R=6/7 [5] R=7/8
Samsung Electronics Co, Ltd. Proprietary Information
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