S5H1420 Datasheet, PDF (10/31 Pages) Samsung semiconductor – Channel Decoder for DVB-S/DSS

S5H1420
DBS Channel Decoder for DVB-S/DSS
The output interface may be forced into high impedance mode by setting MPEG_OEN =0 in the
Address 39. Doing this affects the DATA [7:0], BYTE_CLOCK, SYNC, VALID and ERROR pins. The
output stream is either parallel (byte stream) or serial (bit stream) depending on bit 1 of Address 39.
3.4.8 Spectrum Inverse of Code Rate 5/6
In case of Code Rate 5/6, because of its character, regardless of condition of spectrum it can be locked.
Rest of the code rates except 5/6, if Viterbi is locked, byte becomes sync but in case of code rate 5/6,
even if Viterbi is locked there are chances byte does not become sync. Therefore, in case of Code
Rate 5/6, it should be processed using S/W.
Processing procedure is like below.
1. When the rest is locked except byte sync, code rate check 5/6.
- Code rate monitoring : Addr [0x32], Bit position[0-2]
2. When Code Rate is 5/6, Check inverse spectrum status.
- Spectrum inverse monitoring : Addr [0x32], Bit poisition[3]
3. Inverse inversion spectrum.
- Spectrum inverse setting : Addr [0x31], Bit poisition[3], Set 1
Addr [0x31], Bit poisition[4], Set 1 or 0
3.4.9.1 Parallel output interface
A schematic diagram of the parallel output interface is shown in Figure 4. The parallel output format is
compliant with the DVB-S common interface protocol.
When the byte sync is not found (SYNC_FLAG = 0 in the SYNC02 register), VALID (corresponding to
the MiVAL signal of the DVB-S common interface standard) remains at a low level.
BYTE_CLOCK has a duty cycle between 40 and 60%. The VALID signal is generated depending on bit
2 of Address 39. The BYTE_CLOCK, SYNC, VALID and ERROR signal polarity is controlled
depending on contents in the Register 38.
3.4.9.2 Serial output interface
The serial output interface is shown in Figure5. The serial bit stream is available on D7, where MSB is
first to reconstruct the original order. If MPEG_DOUT = 1, then the parity bits are output (Register 39).
If MPEG_DOUT =0, the data is null during the parity time slots.
SYNC is only high during the first bit of each packet, instead of during the first byte in Parallel mode.
ERROR has the same function as in parallel mode.
BYTE_CLOCK is the serial bit clock; it is same the master clock, fclk. All of the outputs are
synchronous of the same master clock edge. D7, SYNC, VALID and ERROR may be properly sampled
externally by the rising edge of BYTE_CLOCK.
The first bit detected in a valid packet may be decoded if it is found on the appropriate edge of
BYTE_CLOCK, where SYNC = 1, ERROR = 0, VALID = 1. The following bits only require the assertion
of VALID (while VALID = 1,). Outputs D0 to D6 remain at low level in serial mode.
Samsung Electronics Co, Ltd. Proprietary Information
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