S5H1420 Datasheet, PDF (27/31 Pages) Samsung semiconductor – Channel Decoder for DVB-S/DSS

5.5 Timing characteristics
S5H1420
DBS Channel Decoder for DVB-S/DSS
Symbol
Parameter
Min
Typ Max Unit
f_VCO
f_{CLK_IN}
Internal VCO frequency
300
CLK_IN OR XTAL frequency
4
400
MHz
30
MHz
PARALLEL OUTPUT D[7:0], D/P, CLK_OUT, STR_OUT, ERROR OUTPUT CHARACTERITICS
Bit RS=1 in RS CONTROL REGISTER(Address33). Refer to Figure 6
t_{CLK_duty}
t_CKSU
CLK_OUT duty cycle
40
50
60
%
D[7:0], D/P, STR_OUT, ERROR stable before
2*Tm (1)
ns
CLK_OUT Falling Edge
t_CKH
D[7:0], D/P, STR_OUT, ERROR stable
2*Tm (1)
ns
after CLK_OUT Falling Edge
Bit RS=0 in RS CONTROL REGISTER(Address33). Refer to Figure 7
t_CKSU
D[7:0], D/P, STR_OUT, ERROR stable before
2*Tm (1)
ns
CLK_OUT Falling Edge
t_CKH
D[7:0], D/P, STR_OUT, ERROR stable
2*Tm (1)
ns
after CLK_OUT Falling Edge
SERIAL O U T P U T D [ 7 : 0 ] , D / P , C L K _ O U T , S T R _ O U T , E R R O R O U T P U T C H A R A C T E R I T I C S
Bit RS=1 in RS CONTROL REGISTER(Address33). f_CLK= 90MHz. Refer to Figure 8
t_CKSU
D[7:0], D/P, STR_OUT, ERROR stable before
3.5
ns
CLK_OUT Falling Edge
t_CKH
D[7:0], D/P, STR_OUT, ERROR stable
2
ns
after CLK_OUT Falling Edge
Bit RS=0 in RS CONTROL REGISTER(Address33). f_CLK = 90MHz. Refer to Figure 9
t_CKSU
D[7:0], D/P, STR_OUT, ERROR stable before
3.5
ns
CLK_OUT Falling Edge
t_CKH
D[7:0], D/P, STR_OUT, ERROR stable
2
ns
after CLK_OUT Falling Edge
Figure 6
CLK_OUT
Figure 7
CLK_OUT
D[7:0], D/P
STR_OUT,
ERROR
Figure 8
CLK_OUT
t t CKSU
CKH
D[7:0], D/P
STR_OUT,
ERROR
Figure 9
CLK_OUT
t t CKSU
CKH
D[7:0], D/P
STR_OUT,
ERROR
t t CKSU
CKH
D[7:0], D/P
STR_OUT,
ERROR
t t CKSU
CKH
Samsung Electronics Co, Ltd. Proprietary Information
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