S5H1420 Datasheet, PDF (28/31 Pages) Samsung semiconductor – Channel Decoder for DVB-S/DSS

5.6 I²C bus characteristics
S5H1420
DBS Channel Decoder for DVB-S/DSS
Symbol
V_IL
V_IH
V_OH
V_OL
I_LK
C_IN
I_OL
f_SCLN
f_SCLS
t_BUF
t_HD,STA
t_LOW
t_HIGH
t_SU,STA
t_SU,STO
t_SU,DAT
t_R, t_F
C_B
Parameter
Low Level input Voltage
High Level input Voltage
High Level output Voltage
Low Level output Voltage
Input Leakage Current
Input Capacitance
Output Sink Current
SCL Clock Frequency
Bus Free Time between a STOP and START
Condition
Hold Time(repeated)START Condition. After
this period, the first clock pulse is generated
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a repeated START Condition
Setup Time for STOP Condition
Data Setup Time
Rise and Fall Time of both SDA and SCL
signals
Capacitive Load for each Bus Line
Test Condition s Min Typ
Pull up to 5V ±10% - 0.5
2.0
Pull up to 5V ± 10%
VIN = 0V to 5V
0
VOL = 0.5V
Normal Mode
Standby Mode
-10
3.5
10
0
0
1.3
0.6
1.3
0.6
0.6
0.6
100
Max
0.8
5.5
5.5
0.4
10
f_{M_CLK} /40
f_{M_CLK} /10
300
400
Unit
V
V
V
V
uA
pF
mA
_
_
us
us
us
us
us
us
ns
ns
pF
I²C bus timing diagram
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Samsung Electronics Co, Ltd. Proprietary Information
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