M16C63 Datasheet, PDF (98/115 Pages) Renesas Technology Corp – RENESAS MCU

M16C/63 Group
5. Electrical Characteristics
V_CC1 = V_CC2 = 3 V
Switching Characteristics
(V_CC1 = V_CC2 = 3 V, V_SS = 0 V, at T_opr = -20 to 85°C/-40 to 85°C unless otherwise specified)
5.3.4.3 In 2 or 3 Waits Setting, and When Accessing External Area and Using
Multiplexed Bus
Table 5.58 Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When
Accessing External Area and Using Multiplexed Bus) ⁽⁵⁾
Symbol
t_d(BCLK-AD)
t_h(BCLK-AD)
t_h(RD-AD)
t_h(WR-AD)
t_d(BCLK-CS)
t_h(BCLK-CS)
t_h(RD-CS)
t_h(WR-CS)
t_d(BCLK-RD)
t_h(BCLK-RD)
t_d(BCLK-WR)
t_h(BCLK-WR)
t_d(BCLK-DB)
t_h(BCLK-DB)
t_d(DB-WR)
t_h(WR-DB)
t_d(BCLK-HLDA)
t_d(BCLK-ALE)
t_h(BCLK-ALE)
t_d(AD-ALE)
t_h(AD-ALE)
t_d(AD-RD)
t_d(AD-WR)
t_dz(RD-AD)
Parameter
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
Chip select output hold time (in relation to RD)
Chip select output hold time (in relation to WR)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR)
HLDA output delay time
ALE signal output delay time (in relation to BCLK)
ALE signal output hold time (in relation to BCLK)
ALE signal output delay time (in relation to Address)
ALE signal output hold time (in relation to Address)
RD signal output delay from the end of address
WR signal output delay from the end of address
Address output floating start time
Measuring
Condition
Standard
Min.
Max.
Unit
50
ns
0
ns
(Note 1)
ns
(Note 1)
ns
50
ns
0
ns
(Note 1)
ns
(Note 1)
ns
40
ns
0
ns
40
ns
See
0
Figure 5.28
ns
50
ns
0
ns
(Note 2)
ns
(Note 1)
ns
40
ns
25
ns
−4
ns
(Note 3)
ns
(Note 4)
ns
0
ns
0
ns
8
ns
Notes:
1. Calculated according to the BCLK frequency as follows:
0----.-5----×_{-----1---0----}⁹ _{– 10[ns]}
f_(BCLK)
2. Calculated according to the BCLK frequency as follows:
-⁽--ⁿ----–-----0---.-5----⁾---^×-----1---0---⁹- – 50[ns]
f_(BCLK)
n is 2 for 2 waits setting, 3 for 3 waits setting.
3. Calculated according to the BCLK frequency as follows:
0----.-5----×_{-----1---0----}⁹ _{– 40[ns]}
f_(BCLK)
4. Calculated according to the BCLK frequency as follows:
0----.-5----×_{-----1---0----}⁹ _{– 15[ns]}
f_(BCLK)
5. When using multiplexed bus, set f_(BCLK) 12.5 MHz or less.
REJ03B0271-0100 Rev.1.00 Sep 15, 2009
Page 98 of 113